Lines Matching full:hw
57 .hw.init = &(struct clk_init_data){
97 .hw.init = &(struct clk_init_data){
116 .hw.init = &(struct clk_init_data){
120 &meson8b_fixed_pll_dco.hw
163 .hw.init = &(struct clk_init_data){
183 .hw.init = &(struct clk_init_data){
187 &meson8b_hdmi_pll_dco.hw
201 .hw.init = &(struct clk_init_data){
205 &meson8b_hdmi_pll_dco.hw
241 .hw.init = &(struct clk_init_data){
260 .hw.init = &(struct clk_init_data){
264 &meson8b_sys_pll_dco.hw
274 .hw.init = &(struct clk_init_data){
278 &meson8b_fixed_pll.hw
289 .hw.init = &(struct clk_init_data){
293 &meson8b_fclk_div2_div.hw
302 .hw.init = &(struct clk_init_data){
306 &meson8b_fixed_pll.hw
317 .hw.init = &(struct clk_init_data){
321 &meson8b_fclk_div3_div.hw
330 .hw.init = &(struct clk_init_data){
334 &meson8b_fixed_pll.hw
345 .hw.init = &(struct clk_init_data){
349 &meson8b_fclk_div4_div.hw
358 .hw.init = &(struct clk_init_data){
362 &meson8b_fixed_pll.hw
373 .hw.init = &(struct clk_init_data){
377 &meson8b_fclk_div5_div.hw
386 .hw.init = &(struct clk_init_data){
390 &meson8b_fixed_pll.hw
401 .hw.init = &(struct clk_init_data){
405 &meson8b_fclk_div7_div.hw
417 .hw.init = &(struct clk_init_data){
421 &meson8b_fixed_pll.hw
451 .hw.init = &(struct clk_init_data){
455 &meson8b_mpll_prediv.hw
466 .hw.init = &(struct clk_init_data){
470 &meson8b_mpll0_div.hw
496 .hw.init = &(struct clk_init_data){
500 &meson8b_mpll_prediv.hw
511 .hw.init = &(struct clk_init_data){
515 &meson8b_mpll1_div.hw
541 .hw.init = &(struct clk_init_data){
545 &meson8b_mpll_prediv.hw
556 .hw.init = &(struct clk_init_data){
560 &meson8b_mpll2_div.hw
575 .hw.init = &(struct clk_init_data){
584 &meson8b_fclk_div3.hw,
585 &meson8b_fclk_div4.hw,
586 &meson8b_fclk_div5.hw,
598 .hw.init = &(struct clk_init_data){
602 &meson8b_mpeg_clk_sel.hw
613 .hw.init = &(struct clk_init_data){
617 &meson8b_mpeg_clk_div.hw
630 .hw.init = &(struct clk_init_data){
635 { .hw = &meson8b_sys_pll.hw, },
646 .hw.init = &(struct clk_init_data){
650 &meson8b_cpu_in_sel.hw
660 .hw.init = &(struct clk_init_data){
664 &meson8b_cpu_in_sel.hw
691 .hw.init = &(struct clk_init_data){
695 &meson8b_cpu_in_sel.hw
710 .hw.init = &(struct clk_init_data){
720 &meson8b_cpu_in_sel.hw,
721 &meson8b_cpu_in_div2.hw,
722 &meson8b_cpu_scale_div.hw,
735 .hw.init = &(struct clk_init_data){
740 { .hw = &meson8b_cpu_scale_out_sel.hw, },
756 .hw.init = &(struct clk_init_data){
761 { .hw = &meson8b_fclk_div4.hw, },
762 { .hw = &meson8b_fclk_div3.hw, },
763 { .hw = &meson8b_fclk_div5.hw, },
764 { .hw = &meson8b_fclk_div7.hw, },
779 .hw.init = &(struct clk_init_data){
783 &meson8b_nand_clk_sel.hw
795 .hw.init = &(struct clk_init_data){
799 &meson8b_nand_clk_div.hw
809 .hw.init = &(struct clk_init_data){
813 &meson8b_cpu_clk.hw
822 .hw.init = &(struct clk_init_data){
826 &meson8b_cpu_clk.hw
835 .hw.init = &(struct clk_init_data){
839 &meson8b_cpu_clk.hw
848 .hw.init = &(struct clk_init_data){
852 &meson8b_cpu_clk.hw
861 .hw.init = &(struct clk_init_data){
865 &meson8b_cpu_clk.hw
874 .hw.init = &(struct clk_init_data){
878 &meson8b_cpu_clk.hw
887 .hw.init = &(struct clk_init_data){
891 &meson8b_cpu_clk.hw
905 .hw.init = &(struct clk_init_data){
909 &meson8b_cpu_clk_div2.hw,
910 &meson8b_cpu_clk_div3.hw,
911 &meson8b_cpu_clk_div4.hw,
912 &meson8b_cpu_clk_div5.hw,
913 &meson8b_cpu_clk_div6.hw,
914 &meson8b_cpu_clk_div7.hw,
915 &meson8b_cpu_clk_div8.hw,
927 .hw.init = &(struct clk_init_data){
931 &meson8b_apb_clk_sel.hw
944 .hw.init = &(struct clk_init_data){
948 &meson8b_cpu_clk_div2.hw,
949 &meson8b_cpu_clk_div3.hw,
950 &meson8b_cpu_clk_div4.hw,
951 &meson8b_cpu_clk_div5.hw,
952 &meson8b_cpu_clk_div6.hw,
953 &meson8b_cpu_clk_div7.hw,
954 &meson8b_cpu_clk_div8.hw,
966 .hw.init = &(struct clk_init_data){
970 &meson8b_periph_clk_sel.hw
985 .hw.init = &(struct clk_init_data){
989 &meson8b_cpu_clk_div2.hw,
990 &meson8b_cpu_clk_div3.hw,
991 &meson8b_cpu_clk_div4.hw,
992 &meson8b_cpu_clk_div5.hw,
993 &meson8b_cpu_clk_div6.hw,
994 &meson8b_cpu_clk_div7.hw,
995 &meson8b_cpu_clk_div8.hw,
1007 .hw.init = &(struct clk_init_data){
1011 &meson8b_axi_clk_sel.hw
1024 .hw.init = &(struct clk_init_data){
1028 &meson8b_cpu_clk_div2.hw,
1029 &meson8b_cpu_clk_div3.hw,
1030 &meson8b_cpu_clk_div4.hw,
1031 &meson8b_cpu_clk_div5.hw,
1032 &meson8b_cpu_clk_div6.hw,
1033 &meson8b_cpu_clk_div7.hw,
1034 &meson8b_cpu_clk_div8.hw,
1046 .hw.init = &(struct clk_init_data){
1050 &meson8b_l2_dram_clk_sel.hw
1063 .hw.init = &(struct clk_init_data){
1073 &meson8b_hdmi_pll_lvds_out.hw
1085 .hw.init = &(struct clk_init_data){
1089 &meson8b_vid_pll_in_sel.hw
1102 .hw.init = &(struct clk_init_data){
1106 &meson8b_vid_pll_in_en.hw
1119 .hw.init = &(struct clk_init_data){
1123 &meson8b_vid_pll_pre_div.hw
1136 .hw.init = &(struct clk_init_data){
1141 &meson8b_vid_pll_pre_div.hw,
1142 &meson8b_vid_pll_post_div.hw,
1155 .hw.init = &(struct clk_init_data){
1159 &meson8b_vid_pll.hw
1167 &meson8b_vid_pll_final_div.hw,
1168 &meson8b_fclk_div4.hw,
1169 &meson8b_fclk_div3.hw,
1170 &meson8b_fclk_div5.hw,
1171 &meson8b_vid_pll_final_div.hw,
1172 &meson8b_fclk_div7.hw,
1173 &meson8b_mpll1.hw,
1182 .hw.init = &(struct clk_init_data){
1196 .hw.init = &(struct clk_init_data){
1200 &meson8b_vclk_in_sel.hw
1212 .hw.init = &(struct clk_init_data){
1216 &meson8b_vclk_in_en.hw
1228 .hw.init = &(struct clk_init_data){
1232 &meson8b_vclk_en.hw
1242 .hw.init = &(struct clk_init_data){
1246 &meson8b_vclk_en.hw
1258 .hw.init = &(struct clk_init_data){
1262 &meson8b_vclk_div2_div.hw
1272 .hw.init = &(struct clk_init_data){
1276 &meson8b_vclk_en.hw
1288 .hw.init = &(struct clk_init_data){
1292 &meson8b_vclk_div4_div.hw
1302 .hw.init = &(struct clk_init_data){
1306 &meson8b_vclk_en.hw
1318 .hw.init = &(struct clk_init_data){
1322 &meson8b_vclk_div6_div.hw
1332 .hw.init = &(struct clk_init_data){
1336 &meson8b_vclk_en.hw
1348 .hw.init = &(struct clk_init_data){
1352 &meson8b_vclk_div12_div.hw
1365 .hw.init = &(struct clk_init_data){
1379 .hw.init = &(struct clk_init_data){
1383 &meson8b_vclk2_in_sel.hw
1395 .hw.init = &(struct clk_init_data){
1399 &meson8b_vclk2_clk_in_en.hw
1411 .hw.init = &(struct clk_init_data){
1415 &meson8b_vclk2_clk_en.hw
1425 .hw.init = &(struct clk_init_data){
1429 &meson8b_vclk2_clk_en.hw
1441 .hw.init = &(struct clk_init_data){
1445 &meson8b_vclk2_div2_div.hw
1455 .hw.init = &(struct clk_init_data){
1459 &meson8b_vclk2_clk_en.hw
1471 .hw.init = &(struct clk_init_data){
1475 &meson8b_vclk2_div4_div.hw
1485 .hw.init = &(struct clk_init_data){
1489 &meson8b_vclk2_clk_en.hw
1501 .hw.init = &(struct clk_init_data){
1505 &meson8b_vclk2_div6_div.hw
1515 .hw.init = &(struct clk_init_data){
1519 &meson8b_vclk2_clk_en.hw
1531 .hw.init = &(struct clk_init_data){
1535 &meson8b_vclk2_div12_div.hw
1543 &meson8b_vclk_div1_gate.hw,
1544 &meson8b_vclk_div2_div_gate.hw,
1545 &meson8b_vclk_div4_div_gate.hw,
1546 &meson8b_vclk_div6_div_gate.hw,
1547 &meson8b_vclk_div12_div_gate.hw,
1556 .hw.init = &(struct clk_init_data){
1570 .hw.init = &(struct clk_init_data){
1574 &meson8b_cts_enct_sel.hw
1587 .hw.init = &(struct clk_init_data){
1601 .hw.init = &(struct clk_init_data){
1605 &meson8b_cts_encp_sel.hw
1618 .hw.init = &(struct clk_init_data){
1632 .hw.init = &(struct clk_init_data){
1636 &meson8b_cts_enci_sel.hw
1649 .hw.init = &(struct clk_init_data){
1663 .hw.init = &(struct clk_init_data){
1667 &meson8b_hdmi_tx_pixel_sel.hw
1675 &meson8b_vclk2_div1_gate.hw,
1676 &meson8b_vclk2_div2_div_gate.hw,
1677 &meson8b_vclk2_div4_div_gate.hw,
1678 &meson8b_vclk2_div6_div_gate.hw,
1679 &meson8b_vclk2_div12_div_gate.hw,
1688 .hw.init = &(struct clk_init_data){
1702 .hw.init = &(struct clk_init_data){
1706 &meson8b_cts_encl_sel.hw
1719 .hw.init = &(struct clk_init_data){
1733 .hw.init = &(struct clk_init_data){
1737 &meson8b_cts_vdac0_sel.hw
1751 .hw.init = &(struct clk_init_data){
1771 .hw.init = &(struct clk_init_data){
1775 &meson8b_hdmi_sys_sel.hw
1787 .hw.init = &(struct clk_init_data) {
1791 &meson8b_hdmi_sys_div.hw
1808 { .hw = &meson8b_mpll2.hw, },
1809 { .hw = &meson8b_mpll1.hw, },
1810 { .hw = &meson8b_fclk_div7.hw, },
1811 { .hw = &meson8b_fclk_div4.hw, },
1812 { .hw = &meson8b_fclk_div3.hw, },
1813 { .hw = &meson8b_fclk_div5.hw, },
1825 .hw.init = &(struct clk_init_data){
1846 .hw.init = &(struct clk_init_data){
1850 &meson8b_mali_0_sel.hw
1862 .hw.init = &(struct clk_init_data){
1866 &meson8b_mali_0_div.hw
1880 .hw.init = &(struct clk_init_data){
1901 .hw.init = &(struct clk_init_data){
1905 &meson8b_mali_1_sel.hw
1917 .hw.init = &(struct clk_init_data){
1921 &meson8b_mali_1_div.hw
1934 .hw.init = &(struct clk_init_data){
1938 &meson8b_mali_0.hw,
1939 &meson8b_mali_1.hw,
1989 .hw.init = &(struct clk_init_data){
2008 .hw.init = &(struct clk_init_data){
2012 &meson8m2_gp_pll_dco.hw
2020 &meson8b_fclk_div4.hw,
2021 &meson8b_fclk_div3.hw,
2022 &meson8b_fclk_div5.hw,
2023 &meson8b_fclk_div7.hw,
2027 &meson8b_fclk_div4.hw,
2028 &meson8b_fclk_div3.hw,
2029 &meson8b_fclk_div5.hw,
2030 &meson8m2_gp_pll.hw,
2039 .hw.init = &(struct clk_init_data){
2054 .hw.init = &(struct clk_init_data){
2069 .hw.init = &(struct clk_init_data){
2093 .hw.init = &(struct clk_init_data) {
2097 &meson8b_vpu_0_div.hw
2110 .hw.init = &(struct clk_init_data){
2125 .hw.init = &(struct clk_init_data){
2140 .hw.init = &(struct clk_init_data){
2164 .hw.init = &(struct clk_init_data) {
2168 &meson8b_vpu_1_div.hw
2189 .hw.init = &(struct clk_init_data){
2193 &meson8b_vpu_0.hw,
2194 &meson8b_vpu_1.hw,
2202 &meson8b_fclk_div4.hw,
2203 &meson8b_fclk_div3.hw,
2204 &meson8b_fclk_div5.hw,
2205 &meson8b_fclk_div7.hw,
2206 &meson8b_mpll2.hw,
2207 &meson8b_mpll1.hw,
2217 .hw.init = &(struct clk_init_data){
2233 .hw.init = &(struct clk_init_data){
2237 &meson8b_vdec_1_sel.hw
2249 .hw.init = &(struct clk_init_data) {
2253 &meson8b_vdec_1_1_div.hw
2267 .hw.init = &(struct clk_init_data){
2271 &meson8b_vdec_1_sel.hw
2283 .hw.init = &(struct clk_init_data) {
2287 &meson8b_vdec_1_2_div.hw
2301 .hw.init = &(struct clk_init_data){
2305 &meson8b_vdec_1_1.hw,
2306 &meson8b_vdec_1_2.hw,
2320 .hw.init = &(struct clk_init_data){
2336 .hw.init = &(struct clk_init_data){
2340 &meson8b_vdec_hcodec_sel.hw
2352 .hw.init = &(struct clk_init_data) {
2356 &meson8b_vdec_hcodec_div.hw
2370 .hw.init = &(struct clk_init_data){
2386 .hw.init = &(struct clk_init_data){
2390 &meson8b_vdec_2_sel.hw
2402 .hw.init = &(struct clk_init_data) {
2406 &meson8b_vdec_2_div.hw
2420 .hw.init = &(struct clk_init_data){
2436 .hw.init = &(struct clk_init_data){
2440 &meson8b_vdec_hevc_sel.hw
2452 .hw.init = &(struct clk_init_data) {
2456 &meson8b_vdec_hevc_div.hw
2470 .hw.init = &(struct clk_init_data){
2475 &meson8b_vdec_hevc_en.hw
2484 &meson8b_mpll0.hw,
2485 &meson8b_mpll1.hw,
2486 &meson8b_mpll2.hw
2499 .hw.init = &(struct clk_init_data){
2514 .hw.init = &(struct clk_init_data){
2518 &meson8b_cts_amclk_sel.hw
2530 .hw.init = &(struct clk_init_data){
2534 &meson8b_cts_amclk_div.hw
2543 &meson8b_mpll0.hw,
2544 &meson8b_mpll1.hw,
2545 &meson8b_mpll2.hw
2558 .hw.init = &(struct clk_init_data) {
2573 .hw.init = &(struct clk_init_data) {
2577 &meson8b_cts_mclk_i958_sel.hw
2589 .hw.init = &(struct clk_init_data){
2593 &meson8b_cts_mclk_i958_div.hw
2606 .hw.init = &(struct clk_init_data){
2610 &meson8b_cts_amclk.hw,
2611 &meson8b_cts_mclk_i958.hw
2623 MESON_PCLK(_name, _reg, _bit, &meson8b_clk81.hw)
2698 MESON_PCLK(_name, _reg, _bit, &meson8b_aiu_glue.hw)
2700 static MESON_PCLK(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6, &meson8b_aiu.hw);
2718 [CLKID_XTAL] = &meson8b_xtal.hw,
2719 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
2720 [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
2721 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
2722 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
2723 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
2724 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
2725 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
2726 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
2727 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
2728 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
2729 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
2730 [CLKID_CLK81] = &meson8b_clk81.hw,
2731 [CLKID_DDR] = &meson8b_ddr.hw,
2732 [CLKID_DOS] = &meson8b_dos.hw,
2733 [CLKID_ISA] = &meson8b_isa.hw,
2734 [CLKID_PL301] = &meson8b_pl301.hw,
2735 [CLKID_PERIPHS] = &meson8b_periphs.hw,
2736 [CLKID_SPICC] = &meson8b_spicc.hw,
2737 [CLKID_I2C] = &meson8b_i2c.hw,
2738 [CLKID_SAR_ADC] = &meson8b_sar_adc.hw,
2739 [CLKID_SMART_CARD] = &meson8b_smart_card.hw,
2740 [CLKID_RNG0] = &meson8b_rng0.hw,
2741 [CLKID_UART0] = &meson8b_uart0.hw,
2742 [CLKID_SDHC] = &meson8b_sdhc.hw,
2743 [CLKID_STREAM] = &meson8b_stream.hw,
2744 [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw,
2745 [CLKID_SDIO] = &meson8b_sdio.hw,
2746 [CLKID_ABUF] = &meson8b_abuf.hw,
2747 [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw,
2748 [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw,
2749 [CLKID_SPI] = &meson8b_spi.hw,
2750 [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw,
2751 [CLKID_ETH] = &meson8b_eth.hw,
2752 [CLKID_DEMUX] = &meson8b_demux.hw,
2753 [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw,
2754 [CLKID_IEC958] = &meson8b_iec958.hw,
2755 [CLKID_I2S_OUT] = &meson8b_i2s_out.hw,
2756 [CLKID_AMCLK] = &meson8b_amclk.hw,
2757 [CLKID_AIFIFO2] = &meson8b_aififo2.hw,
2758 [CLKID_MIXER] = &meson8b_mixer.hw,
2759 [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw,
2760 [CLKID_ADC] = &meson8b_adc.hw,
2761 [CLKID_BLKMV] = &meson8b_blkmv.hw,
2762 [CLKID_AIU] = &meson8b_aiu.hw,
2763 [CLKID_UART1] = &meson8b_uart1.hw,
2764 [CLKID_G2D] = &meson8b_g2d.hw,
2765 [CLKID_USB0] = &meson8b_usb0.hw,
2766 [CLKID_USB1] = &meson8b_usb1.hw,
2767 [CLKID_RESET] = &meson8b_reset.hw,
2768 [CLKID_NAND] = &meson8b_nand.hw,
2769 [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw,
2770 [CLKID_USB] = &meson8b_usb.hw,
2771 [CLKID_VDIN1] = &meson8b_vdin1.hw,
2772 [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw,
2773 [CLKID_EFUSE] = &meson8b_efuse.hw,
2774 [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw,
2775 [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw,
2776 [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw,
2777 [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw,
2778 [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw,
2779 [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw,
2780 [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
2781 [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw,
2782 [CLKID_DVIN] = &meson8b_dvin.hw,
2783 [CLKID_UART2] = &meson8b_uart2.hw,
2784 [CLKID_SANA] = &meson8b_sana.hw,
2785 [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw,
2786 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
2787 [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw,
2788 [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw,
2789 [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw,
2790 [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw,
2791 [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw,
2792 [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw,
2793 [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw,
2794 [CLKID_DAC_CLK] = &meson8b_dac_clk.hw,
2795 [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw,
2796 [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw,
2797 [CLKID_ENC480P] = &meson8b_enc480p.hw,
2798 [CLKID_RNG1] = &meson8b_rng1.hw,
2799 [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw,
2800 [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw,
2801 [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw,
2802 [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw,
2803 [CLKID_EDP] = &meson8b_edp.hw,
2804 [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw,
2805 [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw,
2806 [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw,
2807 [CLKID_AO_IFACE] = &meson8b_ao_iface.hw,
2808 [CLKID_MPLL0] = &meson8b_mpll0.hw,
2809 [CLKID_MPLL1] = &meson8b_mpll1.hw,
2810 [CLKID_MPLL2] = &meson8b_mpll2.hw,
2811 [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
2812 [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw,
2813 [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw,
2814 [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw,
2815 [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw,
2816 [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw,
2817 [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw,
2818 [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw,
2819 [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw,
2820 [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw,
2821 [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw,
2822 [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw,
2823 [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw,
2824 [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw,
2825 [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw,
2826 [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw,
2827 [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw,
2828 [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw,
2829 [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw,
2830 [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw,
2831 [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw,
2832 [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw,
2833 [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw,
2834 [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw,
2835 [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw,
2836 [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw,
2837 [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw,
2838 [CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw,
2839 [CLKID_APB] = &meson8b_apb_clk_gate.hw,
2840 [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw,
2841 [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw,
2842 [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw,
2843 [CLKID_AXI] = &meson8b_axi_clk_gate.hw,
2844 [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw,
2845 [CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw,
2846 [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw,
2847 [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw,
2848 [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw,
2849 [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw,
2850 [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw,
2851 [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw,
2852 [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
2853 [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
2854 [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
2855 [CLKID_VCLK_EN] = &meson8b_vclk_en.hw,
2856 [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
2857 [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
2858 [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
2859 [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw,
2860 [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
2861 [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw,
2862 [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw,
2863 [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw,
2864 [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
2865 [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
2866 [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
2867 [CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw,
2868 [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
2869 [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
2870 [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
2871 [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw,
2872 [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw,
2873 [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw,
2874 [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw,
2875 [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw,
2876 [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw,
2877 [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw,
2878 [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw,
2879 [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw,
2880 [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw,
2881 [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw,
2882 [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw,
2883 [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw,
2884 [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw,
2885 [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw,
2886 [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw,
2887 [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw,
2888 [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw,
2889 [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw,
2890 [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw,
2891 [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw,
2892 [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw,
2893 [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw,
2894 [CLKID_MALI] = &meson8b_mali_0.hw,
2895 [CLKID_VPU_0_SEL] = &meson8b_vpu_0_sel.hw,
2896 [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
2897 [CLKID_VPU] = &meson8b_vpu_0.hw,
2898 [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw,
2899 [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw,
2900 [CLKID_VDEC_1] = &meson8b_vdec_1_1.hw,
2901 [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw,
2902 [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw,
2903 [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw,
2904 [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw,
2905 [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw,
2906 [CLKID_VDEC_2] = &meson8b_vdec_2.hw,
2907 [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw,
2908 [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
2909 [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
2910 [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
2911 [CLKID_CTS_AMCLK_SEL] = &meson8b_cts_amclk_sel.hw,
2912 [CLKID_CTS_AMCLK_DIV] = &meson8b_cts_amclk_div.hw,
2913 [CLKID_CTS_AMCLK] = &meson8b_cts_amclk.hw,
2914 [CLKID_CTS_MCLK_I958_SEL] = &meson8b_cts_mclk_i958_sel.hw,
2915 [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw,
2916 [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw,
2917 [CLKID_CTS_I958] = &meson8b_cts_i958.hw,
2925 [CLKID_XTAL] = &meson8b_xtal.hw,
2926 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
2927 [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
2928 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
2929 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
2930 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
2931 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
2932 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
2933 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
2934 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
2935 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
2936 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
2937 [CLKID_CLK81] = &meson8b_clk81.hw,
2938 [CLKID_DDR] = &meson8b_ddr.hw,
2939 [CLKID_DOS] = &meson8b_dos.hw,
2940 [CLKID_ISA] = &meson8b_isa.hw,
2941 [CLKID_PL301] = &meson8b_pl301.hw,
2942 [CLKID_PERIPHS] = &meson8b_periphs.hw,
2943 [CLKID_SPICC] = &meson8b_spicc.hw,
2944 [CLKID_I2C] = &meson8b_i2c.hw,
2945 [CLKID_SAR_ADC] = &meson8b_sar_adc.hw,
2946 [CLKID_SMART_CARD] = &meson8b_smart_card.hw,
2947 [CLKID_RNG0] = &meson8b_rng0.hw,
2948 [CLKID_UART0] = &meson8b_uart0.hw,
2949 [CLKID_SDHC] = &meson8b_sdhc.hw,
2950 [CLKID_STREAM] = &meson8b_stream.hw,
2951 [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw,
2952 [CLKID_SDIO] = &meson8b_sdio.hw,
2953 [CLKID_ABUF] = &meson8b_abuf.hw,
2954 [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw,
2955 [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw,
2956 [CLKID_SPI] = &meson8b_spi.hw,
2957 [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw,
2958 [CLKID_ETH] = &meson8b_eth.hw,
2959 [CLKID_DEMUX] = &meson8b_demux.hw,
2960 [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw,
2961 [CLKID_IEC958] = &meson8b_iec958.hw,
2962 [CLKID_I2S_OUT] = &meson8b_i2s_out.hw,
2963 [CLKID_AMCLK] = &meson8b_amclk.hw,
2964 [CLKID_AIFIFO2] = &meson8b_aififo2.hw,
2965 [CLKID_MIXER] = &meson8b_mixer.hw,
2966 [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw,
2967 [CLKID_ADC] = &meson8b_adc.hw,
2968 [CLKID_BLKMV] = &meson8b_blkmv.hw,
2969 [CLKID_AIU] = &meson8b_aiu.hw,
2970 [CLKID_UART1] = &meson8b_uart1.hw,
2971 [CLKID_G2D] = &meson8b_g2d.hw,
2972 [CLKID_USB0] = &meson8b_usb0.hw,
2973 [CLKID_USB1] = &meson8b_usb1.hw,
2974 [CLKID_RESET] = &meson8b_reset.hw,
2975 [CLKID_NAND] = &meson8b_nand.hw,
2976 [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw,
2977 [CLKID_USB] = &meson8b_usb.hw,
2978 [CLKID_VDIN1] = &meson8b_vdin1.hw,
2979 [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw,
2980 [CLKID_EFUSE] = &meson8b_efuse.hw,
2981 [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw,
2982 [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw,
2983 [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw,
2984 [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw,
2985 [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw,
2986 [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw,
2987 [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
2988 [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw,
2989 [CLKID_DVIN] = &meson8b_dvin.hw,
2990 [CLKID_UART2] = &meson8b_uart2.hw,
2991 [CLKID_SANA] = &meson8b_sana.hw,
2992 [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw,
2993 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
2994 [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw,
2995 [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw,
2996 [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw,
2997 [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw,
2998 [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw,
2999 [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw,
3000 [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw,
3001 [CLKID_DAC_CLK] = &meson8b_dac_clk.hw,
3002 [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw,
3003 [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw,
3004 [CLKID_ENC480P] = &meson8b_enc480p.hw,
3005 [CLKID_RNG1] = &meson8b_rng1.hw,
3006 [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw,
3007 [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw,
3008 [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw,
3009 [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw,
3010 [CLKID_EDP] = &meson8b_edp.hw,
3011 [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw,
3012 [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw,
3013 [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw,
3014 [CLKID_AO_IFACE] = &meson8b_ao_iface.hw,
3015 [CLKID_MPLL0] = &meson8b_mpll0.hw,
3016 [CLKID_MPLL1] = &meson8b_mpll1.hw,
3017 [CLKID_MPLL2] = &meson8b_mpll2.hw,
3018 [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
3019 [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw,
3020 [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw,
3021 [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw,
3022 [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw,
3023 [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw,
3024 [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw,
3025 [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw,
3026 [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw,
3027 [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw,
3028 [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw,
3029 [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw,
3030 [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw,
3031 [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw,
3032 [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw,
3033 [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw,
3034 [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw,
3035 [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw,
3036 [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw,
3037 [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw,
3038 [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw,
3039 [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw,
3040 [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw,
3041 [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw,
3042 [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw,
3043 [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw,
3044 [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw,
3045 [CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw,
3046 [CLKID_APB] = &meson8b_apb_clk_gate.hw,
3047 [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw,
3048 [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw,
3049 [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw,
3050 [CLKID_AXI] = &meson8b_axi_clk_gate.hw,
3051 [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw,
3052 [CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw,
3053 [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw,
3054 [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw,
3055 [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw,
3056 [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw,
3057 [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw,
3058 [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw,
3059 [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
3060 [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
3061 [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
3062 [CLKID_VCLK_EN] = &meson8b_vclk_en.hw,
3063 [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
3064 [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
3065 [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
3066 [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw,
3067 [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
3068 [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw,
3069 [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw,
3070 [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw,
3071 [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
3072 [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
3073 [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
3074 [CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw,
3075 [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
3076 [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
3077 [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
3078 [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw,
3079 [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw,
3080 [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw,
3081 [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw,
3082 [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw,
3083 [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw,
3084 [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw,
3085 [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw,
3086 [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw,
3087 [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw,
3088 [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw,
3089 [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw,
3090 [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw,
3091 [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw,
3092 [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw,
3093 [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw,
3094 [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw,
3095 [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw,
3096 [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw,
3097 [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw,
3098 [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw,
3099 [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw,
3100 [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw,
3101 [CLKID_MALI_0] = &meson8b_mali_0.hw,
3102 [CLKID_MALI_1_SEL] = &meson8b_mali_1_sel.hw,
3103 [CLKID_MALI_1_DIV] = &meson8b_mali_1_div.hw,
3104 [CLKID_MALI_1] = &meson8b_mali_1.hw,
3105 [CLKID_MALI] = &meson8b_mali.hw,
3106 [CLKID_VPU_0_SEL] = &meson8b_vpu_0_sel.hw,
3107 [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
3108 [CLKID_VPU_0] = &meson8b_vpu_0.hw,
3109 [CLKID_VPU_1_SEL] = &meson8b_vpu_1_sel.hw,
3110 [CLKID_VPU_1_DIV] = &meson8b_vpu_1_div.hw,
3111 [CLKID_VPU_1] = &meson8b_vpu_1.hw,
3112 [CLKID_VPU] = &meson8b_vpu.hw,
3113 [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw,
3114 [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw,
3115 [CLKID_VDEC_1_1] = &meson8b_vdec_1_1.hw,
3116 [CLKID_VDEC_1_2_DIV] = &meson8b_vdec_1_2_div.hw,
3117 [CLKID_VDEC_1_2] = &meson8b_vdec_1_2.hw,
3118 [CLKID_VDEC_1] = &meson8b_vdec_1.hw,
3119 [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw,
3120 [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw,
3121 [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw,
3122 [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw,
3123 [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw,
3124 [CLKID_VDEC_2] = &meson8b_vdec_2.hw,
3125 [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw,
3126 [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
3127 [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
3128 [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
3129 [CLKID_CTS_AMCLK_SEL] = &meson8b_cts_amclk_sel.hw,
3130 [CLKID_CTS_AMCLK_DIV] = &meson8b_cts_amclk_div.hw,
3131 [CLKID_CTS_AMCLK] = &meson8b_cts_amclk.hw,
3132 [CLKID_CTS_MCLK_I958_SEL] = &meson8b_cts_mclk_i958_sel.hw,
3133 [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw,
3134 [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw,
3135 [CLKID_CTS_I958] = &meson8b_cts_i958.hw,
3143 [CLKID_XTAL] = &meson8b_xtal.hw,
3144 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
3145 [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
3146 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
3147 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
3148 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
3149 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
3150 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
3151 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
3152 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
3153 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
3154 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
3155 [CLKID_CLK81] = &meson8b_clk81.hw,
3156 [CLKID_DDR] = &meson8b_ddr.hw,
3157 [CLKID_DOS] = &meson8b_dos.hw,
3158 [CLKID_ISA] = &meson8b_isa.hw,
3159 [CLKID_PL301] = &meson8b_pl301.hw,
3160 [CLKID_PERIPHS] = &meson8b_periphs.hw,
3161 [CLKID_SPICC] = &meson8b_spicc.hw,
3162 [CLKID_I2C] = &meson8b_i2c.hw,
3163 [CLKID_SAR_ADC] = &meson8b_sar_adc.hw,
3164 [CLKID_SMART_CARD] = &meson8b_smart_card.hw,
3165 [CLKID_RNG0] = &meson8b_rng0.hw,
3166 [CLKID_UART0] = &meson8b_uart0.hw,
3167 [CLKID_SDHC] = &meson8b_sdhc.hw,
3168 [CLKID_STREAM] = &meson8b_stream.hw,
3169 [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw,
3170 [CLKID_SDIO] = &meson8b_sdio.hw,
3171 [CLKID_ABUF] = &meson8b_abuf.hw,
3172 [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw,
3173 [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw,
3174 [CLKID_SPI] = &meson8b_spi.hw,
3175 [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw,
3176 [CLKID_ETH] = &meson8b_eth.hw,
3177 [CLKID_DEMUX] = &meson8b_demux.hw,
3178 [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw,
3179 [CLKID_IEC958] = &meson8b_iec958.hw,
3180 [CLKID_I2S_OUT] = &meson8b_i2s_out.hw,
3181 [CLKID_AMCLK] = &meson8b_amclk.hw,
3182 [CLKID_AIFIFO2] = &meson8b_aififo2.hw,
3183 [CLKID_MIXER] = &meson8b_mixer.hw,
3184 [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw,
3185 [CLKID_ADC] = &meson8b_adc.hw,
3186 [CLKID_BLKMV] = &meson8b_blkmv.hw,
3187 [CLKID_AIU] = &meson8b_aiu.hw,
3188 [CLKID_UART1] = &meson8b_uart1.hw,
3189 [CLKID_G2D] = &meson8b_g2d.hw,
3190 [CLKID_USB0] = &meson8b_usb0.hw,
3191 [CLKID_USB1] = &meson8b_usb1.hw,
3192 [CLKID_RESET] = &meson8b_reset.hw,
3193 [CLKID_NAND] = &meson8b_nand.hw,
3194 [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw,
3195 [CLKID_USB] = &meson8b_usb.hw,
3196 [CLKID_VDIN1] = &meson8b_vdin1.hw,
3197 [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw,
3198 [CLKID_EFUSE] = &meson8b_efuse.hw,
3199 [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw,
3200 [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw,
3201 [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw,
3202 [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw,
3203 [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw,
3204 [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw,
3205 [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
3206 [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw,
3207 [CLKID_DVIN] = &meson8b_dvin.hw,
3208 [CLKID_UART2] = &meson8b_uart2.hw,
3209 [CLKID_SANA] = &meson8b_sana.hw,
3210 [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw,
3211 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
3212 [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw,
3213 [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw,
3214 [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw,
3215 [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw,
3216 [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw,
3217 [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw,
3218 [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw,
3219 [CLKID_DAC_CLK] = &meson8b_dac_clk.hw,
3220 [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw,
3221 [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw,
3222 [CLKID_ENC480P] = &meson8b_enc480p.hw,
3223 [CLKID_RNG1] = &meson8b_rng1.hw,
3224 [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw,
3225 [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw,
3226 [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw,
3227 [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw,
3228 [CLKID_EDP] = &meson8b_edp.hw,
3229 [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw,
3230 [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw,
3231 [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw,
3232 [CLKID_AO_IFACE] = &meson8b_ao_iface.hw,
3233 [CLKID_MPLL0] = &meson8b_mpll0.hw,
3234 [CLKID_MPLL1] = &meson8b_mpll1.hw,
3235 [CLKID_MPLL2] = &meson8b_mpll2.hw,
3236 [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
3237 [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw,
3238 [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw,
3239 [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw,
3240 [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw,
3241 [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw,
3242 [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw,
3243 [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw,
3244 [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw,
3245 [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw,
3246 [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw,
3247 [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw,
3248 [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw,
3249 [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw,
3250 [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw,
3251 [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw,
3252 [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw,
3253 [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw,
3254 [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw,
3255 [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw,
3256 [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw,
3257 [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw,
3258 [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw,
3259 [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw,
3260 [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw,
3261 [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw,
3262 [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw,
3263 [CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw,
3264 [CLKID_APB] = &meson8b_apb_clk_gate.hw,
3265 [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw,
3266 [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw,
3267 [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw,
3268 [CLKID_AXI] = &meson8b_axi_clk_gate.hw,
3269 [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw,
3270 [CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw,
3271 [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw,
3272 [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw,
3273 [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw,
3274 [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw,
3275 [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw,
3276 [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw,
3277 [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
3278 [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
3279 [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
3280 [CLKID_VCLK_EN] = &meson8b_vclk_en.hw,
3281 [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
3282 [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
3283 [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
3284 [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw,
3285 [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
3286 [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw,
3287 [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw,
3288 [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw,
3289 [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
3290 [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
3291 [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
3292 [CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw,
3293 [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
3294 [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
3295 [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
3296 [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw,
3297 [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw,
3298 [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw,
3299 [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw,
3300 [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw,
3301 [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw,
3302 [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw,
3303 [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw,
3304 [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw,
3305 [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw,
3306 [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw,
3307 [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw,
3308 [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw,
3309 [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw,
3310 [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw,
3311 [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw,
3312 [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw,
3313 [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw,
3314 [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw,
3315 [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw,
3316 [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw,
3317 [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw,
3318 [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw,
3319 [CLKID_MALI_0] = &meson8b_mali_0.hw,
3320 [CLKID_MALI_1_SEL] = &meson8b_mali_1_sel.hw,
3321 [CLKID_MALI_1_DIV] = &meson8b_mali_1_div.hw,
3322 [CLKID_MALI_1] = &meson8b_mali_1.hw,
3323 [CLKID_MALI] = &meson8b_mali.hw,
3324 [CLKID_GP_PLL_DCO] = &meson8m2_gp_pll_dco.hw,
3325 [CLKID_GP_PLL] = &meson8m2_gp_pll.hw,
3326 [CLKID_VPU_0_SEL] = &meson8m2_vpu_0_sel.hw,
3327 [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
3328 [CLKID_VPU_0] = &meson8b_vpu_0.hw,
3329 [CLKID_VPU_1_SEL] = &meson8m2_vpu_1_sel.hw,
3330 [CLKID_VPU_1_DIV] = &meson8b_vpu_1_div.hw,
3331 [CLKID_VPU_1] = &meson8b_vpu_1.hw,
3332 [CLKID_VPU] = &meson8b_vpu.hw,
3333 [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw,
3334 [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw,
3335 [CLKID_VDEC_1_1] = &meson8b_vdec_1_1.hw,
3336 [CLKID_VDEC_1_2_DIV] = &meson8b_vdec_1_2_div.hw,
3337 [CLKID_VDEC_1_2] = &meson8b_vdec_1_2.hw,
3338 [CLKID_VDEC_1] = &meson8b_vdec_1.hw,
3339 [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw,
3340 [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw,
3341 [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw,
3342 [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw,
3343 [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw,
3344 [CLKID_VDEC_2] = &meson8b_vdec_2.hw,
3345 [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw,
3346 [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
3347 [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
3348 [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
3349 [CLKID_CTS_AMCLK_SEL] = &meson8b_cts_amclk_sel.hw,
3350 [CLKID_CTS_AMCLK_DIV] = &meson8b_cts_amclk_div.hw,
3351 [CLKID_CTS_AMCLK] = &meson8b_cts_amclk.hw,
3352 [CLKID_CTS_MCLK_I958_SEL] = &meson8b_cts_mclk_i958_sel.hw,
3353 [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw,
3354 [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw,
3355 [CLKID_CTS_I958] = &meson8b_cts_i958.hw,
3807 notifier_clk_name = clk_hw_get_name(&meson8b_cpu_scale_out_sel.hw); in meson8b_clkc_init_common()