Lines Matching full:hw
62 .hw.init = &(struct clk_init_data){
79 .hw.init = &(struct clk_init_data){
83 &g12a_fixed_pll_dco.hw
127 .hw.init = &(struct clk_init_data){
146 .hw.init = &(struct clk_init_data){
150 &g12a_sys_pll_dco.hw
186 .hw.init = &(struct clk_init_data){
205 .hw.init = &(struct clk_init_data){
209 &g12b_sys1_pll_dco.hw
221 .hw.init = &(struct clk_init_data) {
224 .parent_hws = (const struct clk_hw *[]) { &g12a_sys_pll.hw },
238 .hw.init = &(struct clk_init_data) {
242 &g12b_sys1_pll.hw
255 .hw.init = &(struct clk_init_data){
259 &g12a_sys_pll_div16_en.hw
268 .hw.init = &(struct clk_init_data){
272 &g12b_sys1_pll_div16_en.hw
281 .hw.init = &(struct clk_init_data){
284 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
294 .hw.init = &(struct clk_init_data){
298 &g12a_fclk_div2_div.hw
318 .hw.init = &(struct clk_init_data){
321 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
331 .hw.init = &(struct clk_init_data){
335 &g12a_fclk_div3_div.hw
359 .hw.init = &(struct clk_init_data){
364 { .hw = &g12a_fclk_div2.hw },
365 { .hw = &g12a_fclk_div3.hw },
379 .hw.init = &(struct clk_init_data){
384 { .hw = &g12a_fclk_div2.hw },
385 { .hw = &g12a_fclk_div3.hw },
407 .hw.init = &(struct clk_init_data){
411 &g12a_cpu_clk_premux0.hw
426 .hw.init = &(struct clk_init_data){
430 &g12a_cpu_clk_premux0.hw,
431 &g12a_cpu_clk_mux0_div.hw,
445 .hw.init = &(struct clk_init_data){
449 &g12a_cpu_clk_premux1.hw
462 .hw.init = &(struct clk_init_data){
466 &g12a_cpu_clk_premux1.hw,
467 &g12a_cpu_clk_mux1_div.hw,
483 .hw.init = &(struct clk_init_data){
487 &g12a_cpu_clk_postmux0.hw,
488 &g12a_cpu_clk_postmux1.hw,
503 .hw.init = &(struct clk_init_data){
507 &g12a_cpu_clk_dyn.hw,
508 &g12a_sys_pll.hw,
523 .hw.init = &(struct clk_init_data){
527 &g12a_cpu_clk_dyn.hw,
528 &g12b_sys1_pll.hw
543 .hw.init = &(struct clk_init_data){
548 { .hw = &g12a_fclk_div2.hw },
549 { .hw = &g12a_fclk_div3.hw },
570 .hw.init = &(struct clk_init_data){
574 &g12b_cpub_clk_premux0.hw
589 .hw.init = &(struct clk_init_data){
593 &g12b_cpub_clk_premux0.hw,
594 &g12b_cpub_clk_mux0_div.hw
608 .hw.init = &(struct clk_init_data){
613 { .hw = &g12a_fclk_div2.hw },
614 { .hw = &g12a_fclk_div3.hw },
629 .hw.init = &(struct clk_init_data){
633 &g12b_cpub_clk_premux1.hw
646 .hw.init = &(struct clk_init_data){
650 &g12b_cpub_clk_premux1.hw,
651 &g12b_cpub_clk_mux1_div.hw
667 .hw.init = &(struct clk_init_data){
671 &g12b_cpub_clk_postmux0.hw,
672 &g12b_cpub_clk_postmux1.hw
687 .hw.init = &(struct clk_init_data){
691 &g12b_cpub_clk_dyn.hw,
692 &g12a_sys_pll.hw
708 .hw.init = &(struct clk_init_data){
713 { .hw = &g12a_fclk_div2.hw },
714 { .hw = &g12a_fclk_div3.hw },
715 { .hw = &sm1_gp1_pll.hw },
728 .hw.init = &(struct clk_init_data){
733 { .hw = &g12a_fclk_div2.hw },
734 { .hw = &g12a_fclk_div3.hw },
735 { .hw = &sm1_gp1_pll.hw },
748 .hw.init = &(struct clk_init_data){
752 &sm1_dsu_clk_premux0.hw
765 .hw.init = &(struct clk_init_data){
769 &sm1_dsu_clk_premux0.hw,
770 &sm1_dsu_clk_mux0_div.hw,
783 .hw.init = &(struct clk_init_data){
787 &sm1_dsu_clk_premux1.hw
800 .hw.init = &(struct clk_init_data){
804 &sm1_dsu_clk_premux1.hw,
805 &sm1_dsu_clk_mux1_div.hw,
818 .hw.init = &(struct clk_init_data){
822 &sm1_dsu_clk_postmux0.hw,
823 &sm1_dsu_clk_postmux1.hw,
836 .hw.init = &(struct clk_init_data){
840 &sm1_dsu_clk_dyn.hw,
841 &g12a_sys_pll.hw,
854 .hw.init = &(struct clk_init_data){
858 &g12a_cpu_clk.hw,
872 .hw.init = &(struct clk_init_data){
876 &g12a_cpu_clk.hw,
890 .hw.init = &(struct clk_init_data){
894 &g12a_cpu_clk.hw,
908 .hw.init = &(struct clk_init_data){
912 &g12a_cpu_clk.hw,
913 &sm1_dsu_final_clk.hw,
1025 .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1026 .cpu_clk_postmux0 = &g12a_cpu_clk_postmux0.hw,
1027 .cpu_clk_postmux1 = &g12a_cpu_clk_postmux1.hw,
1028 .cpu_clk_premux1 = &g12a_cpu_clk_premux1.hw,
1033 .cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,
1034 .cpu_clk_postmux0 = &g12b_cpub_clk_postmux0.hw,
1035 .cpu_clk_postmux1 = &g12b_cpub_clk_postmux1.hw,
1036 .cpu_clk_premux1 = &g12b_cpub_clk_premux1.hw,
1108 .sys_pll = &g12a_sys_pll.hw,
1109 .cpu_clk = &g12a_cpu_clk.hw,
1110 .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1116 .sys_pll = &g12b_sys1_pll.hw,
1117 .cpu_clk = &g12b_cpu_clk.hw,
1118 .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1124 .sys_pll = &g12a_sys_pll.hw,
1125 .cpu_clk = &g12b_cpub_clk.hw,
1126 .cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,
1135 .hw.init = &(struct clk_init_data) {
1139 &g12a_cpu_clk.hw
1154 .hw.init = &(struct clk_init_data) {
1158 &g12b_cpub_clk.hw
1171 .hw.init = &(struct clk_init_data){
1175 &g12a_cpu_clk_div16_en.hw
1184 .hw.init = &(struct clk_init_data){
1188 &g12b_cpub_clk_div16_en.hw
1201 .hw.init = &(struct clk_init_data){
1204 .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
1214 .hw.init = &(struct clk_init_data) {
1218 &g12a_cpu_clk_apb_div.hw
1235 .hw.init = &(struct clk_init_data){
1238 .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
1248 .hw.init = &(struct clk_init_data) {
1252 &g12a_cpu_clk_atb_div.hw
1269 .hw.init = &(struct clk_init_data){
1272 .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
1282 .hw.init = &(struct clk_init_data) {
1286 &g12a_cpu_clk_axi_div.hw
1303 .hw.init = &(struct clk_init_data){
1326 .hw.init = &(struct clk_init_data) {
1330 &g12a_cpu_clk_trace_div.hw
1343 .hw.init = &(struct clk_init_data){
1347 &g12b_cpub_clk.hw
1356 .hw.init = &(struct clk_init_data){
1360 &g12b_cpub_clk.hw
1369 .hw.init = &(struct clk_init_data){
1373 &g12b_cpub_clk.hw
1382 .hw.init = &(struct clk_init_data){
1386 &g12b_cpub_clk.hw
1395 .hw.init = &(struct clk_init_data){
1399 &g12b_cpub_clk.hw
1408 .hw.init = &(struct clk_init_data){
1412 &g12b_cpub_clk.hw
1421 .hw.init = &(struct clk_init_data){
1425 &g12b_cpub_clk.hw
1439 .hw.init = &(struct clk_init_data){
1443 &g12b_cpub_clk_div2.hw,
1444 &g12b_cpub_clk_div3.hw,
1445 &g12b_cpub_clk_div4.hw,
1446 &g12b_cpub_clk_div5.hw,
1447 &g12b_cpub_clk_div6.hw,
1448 &g12b_cpub_clk_div7.hw,
1449 &g12b_cpub_clk_div8.hw
1461 .hw.init = &(struct clk_init_data) {
1465 &g12b_cpub_clk_apb_sel.hw
1482 .hw.init = &(struct clk_init_data){
1486 &g12b_cpub_clk_div2.hw,
1487 &g12b_cpub_clk_div3.hw,
1488 &g12b_cpub_clk_div4.hw,
1489 &g12b_cpub_clk_div5.hw,
1490 &g12b_cpub_clk_div6.hw,
1491 &g12b_cpub_clk_div7.hw,
1492 &g12b_cpub_clk_div8.hw
1504 .hw.init = &(struct clk_init_data) {
1508 &g12b_cpub_clk_atb_sel.hw
1525 .hw.init = &(struct clk_init_data){
1529 &g12b_cpub_clk_div2.hw,
1530 &g12b_cpub_clk_div3.hw,
1531 &g12b_cpub_clk_div4.hw,
1532 &g12b_cpub_clk_div5.hw,
1533 &g12b_cpub_clk_div6.hw,
1534 &g12b_cpub_clk_div7.hw,
1535 &g12b_cpub_clk_div8.hw
1547 .hw.init = &(struct clk_init_data) {
1551 &g12b_cpub_clk_axi_sel.hw
1568 .hw.init = &(struct clk_init_data){
1572 &g12b_cpub_clk_div2.hw,
1573 &g12b_cpub_clk_div3.hw,
1574 &g12b_cpub_clk_div4.hw,
1575 &g12b_cpub_clk_div5.hw,
1576 &g12b_cpub_clk_div6.hw,
1577 &g12b_cpub_clk_div7.hw,
1578 &g12b_cpub_clk_div8.hw
1590 .hw.init = &(struct clk_init_data) {
1594 &g12b_cpub_clk_trace_sel.hw
1657 .hw.init = &(struct clk_init_data){
1675 .hw.init = &(struct clk_init_data){
1679 &g12a_gp0_pll_dco.hw
1719 .hw.init = &(struct clk_init_data){
1739 .hw.init = &(struct clk_init_data){
1743 &sm1_gp1_pll_dco.hw
1798 .hw.init = &(struct clk_init_data){
1816 .hw.init = &(struct clk_init_data){
1820 &g12a_hifi_pll_dco.hw
1889 .hw.init = &(struct clk_init_data){
1902 .hw.init = &(struct clk_init_data){
1906 &g12a_pcie_pll_dco.hw
1922 .hw.init = &(struct clk_init_data){
1926 &g12a_pcie_pll_dco_div2.hw
1936 .hw.init = &(struct clk_init_data){
1940 &g12a_pcie_pll_od.hw
1980 .hw.init = &(struct clk_init_data){
2002 .hw.init = &(struct clk_init_data){
2006 &g12a_hdmi_pll_dco.hw
2020 .hw.init = &(struct clk_init_data){
2024 &g12a_hdmi_pll_od.hw
2038 .hw.init = &(struct clk_init_data){
2042 &g12a_hdmi_pll_od2.hw
2052 .hw.init = &(struct clk_init_data){
2055 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
2065 .hw.init = &(struct clk_init_data){
2069 &g12a_fclk_div4_div.hw
2078 .hw.init = &(struct clk_init_data){
2081 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
2091 .hw.init = &(struct clk_init_data){
2095 &g12a_fclk_div5_div.hw
2104 .hw.init = &(struct clk_init_data){
2107 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
2117 .hw.init = &(struct clk_init_data){
2121 &g12a_fclk_div7_div.hw
2130 .hw.init = &(struct clk_init_data){
2134 &g12a_fixed_pll_dco.hw
2145 .hw.init = &(struct clk_init_data){
2149 &g12a_fclk_div2p5_div.hw
2158 .hw.init = &(struct clk_init_data){
2162 &g12a_fixed_pll_dco.hw
2174 .hw.init = &(struct clk_init_data){
2179 { .hw = &g12a_mpll_50m_div.hw },
2188 .hw.init = &(struct clk_init_data){
2192 &g12a_fixed_pll_dco.hw
2228 .hw.init = &(struct clk_init_data){
2232 &g12a_mpll_prediv.hw
2243 .hw.init = &(struct clk_init_data){
2246 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll0_div.hw },
2282 .hw.init = &(struct clk_init_data){
2286 &g12a_mpll_prediv.hw
2297 .hw.init = &(struct clk_init_data){
2300 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll1_div.hw },
2336 .hw.init = &(struct clk_init_data){
2340 &g12a_mpll_prediv.hw
2351 .hw.init = &(struct clk_init_data){
2354 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll2_div.hw },
2390 .hw.init = &(struct clk_init_data){
2394 &g12a_mpll_prediv.hw
2405 .hw.init = &(struct clk_init_data){
2408 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll3_div.hw },
2417 { .hw = &g12a_fclk_div7.hw },
2418 { .hw = &g12a_mpll1.hw },
2419 { .hw = &g12a_mpll2.hw },
2420 { .hw = &g12a_fclk_div4.hw },
2421 { .hw = &g12a_fclk_div3.hw },
2422 { .hw = &g12a_fclk_div5.hw },
2432 .hw.init = &(struct clk_init_data){
2446 .hw.init = &(struct clk_init_data){
2450 &g12a_mpeg_clk_sel.hw
2462 .hw.init = &(struct clk_init_data){
2466 &g12a_mpeg_clk_div.hw
2475 { .hw = &g12a_fclk_div2.hw },
2476 { .hw = &g12a_fclk_div3.hw },
2477 { .hw = &g12a_fclk_div5.hw },
2478 { .hw = &g12a_fclk_div7.hw },
2494 .hw.init = &(struct clk_init_data) {
2509 .hw.init = &(struct clk_init_data) {
2513 &g12a_sd_emmc_a_clk0_sel.hw
2525 .hw.init = &(struct clk_init_data){
2529 &g12a_sd_emmc_a_clk0_div.hw
2543 .hw.init = &(struct clk_init_data) {
2558 .hw.init = &(struct clk_init_data) {
2562 &g12a_sd_emmc_b_clk0_sel.hw
2574 .hw.init = &(struct clk_init_data){
2578 &g12a_sd_emmc_b_clk0_div.hw
2592 .hw.init = &(struct clk_init_data) {
2607 .hw.init = &(struct clk_init_data) {
2611 &g12a_sd_emmc_c_clk0_sel.hw
2623 .hw.init = &(struct clk_init_data){
2627 &g12a_sd_emmc_c_clk0_div.hw
2649 .hw.init = &(struct clk_init_data) {
2652 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_pll.hw },
2659 &g12a_vid_pll_div.hw,
2660 &g12a_hdmi_pll.hw,
2669 .hw.init = &(struct clk_init_data){
2687 .hw.init = &(struct clk_init_data) {
2691 &g12a_vid_pll_sel.hw
2701 &g12a_fclk_div3.hw,
2702 &g12a_fclk_div4.hw,
2703 &g12a_fclk_div5.hw,
2704 &g12a_fclk_div7.hw,
2705 &g12a_mpll1.hw,
2706 &g12a_vid_pll.hw,
2707 &g12a_hifi_pll.hw,
2708 &g12a_gp0_pll.hw,
2717 .hw.init = &(struct clk_init_data){
2732 .hw.init = &(struct clk_init_data){
2735 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_sel.hw },
2746 .hw.init = &(struct clk_init_data) {
2749 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_div.hw },
2761 .hw.init = &(struct clk_init_data){
2776 .hw.init = &(struct clk_init_data){
2779 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_sel.hw },
2790 .hw.init = &(struct clk_init_data) {
2793 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_div.hw },
2805 .hw.init = &(struct clk_init_data){
2813 &g12a_vpu_0.hw,
2814 &g12a_vpu_1.hw,
2824 &g12a_fclk_div2p5.hw,
2825 &g12a_fclk_div3.hw,
2826 &g12a_fclk_div4.hw,
2827 &g12a_fclk_div5.hw,
2828 &g12a_fclk_div7.hw,
2829 &g12a_hifi_pll.hw,
2830 &g12a_gp0_pll.hw,
2840 .hw.init = &(struct clk_init_data){
2856 .hw.init = &(struct clk_init_data){
2860 &g12a_vdec_1_sel.hw
2872 .hw.init = &(struct clk_init_data) {
2876 &g12a_vdec_1_div.hw
2890 .hw.init = &(struct clk_init_data){
2906 .hw.init = &(struct clk_init_data){
2910 &g12a_vdec_hevcf_sel.hw
2922 .hw.init = &(struct clk_init_data) {
2926 &g12a_vdec_hevcf_div.hw
2940 .hw.init = &(struct clk_init_data){
2956 .hw.init = &(struct clk_init_data){
2960 &g12a_vdec_hevc_sel.hw
2972 .hw.init = &(struct clk_init_data) {
2976 &g12a_vdec_hevc_div.hw
2986 &g12a_fclk_div4.hw,
2987 &g12a_fclk_div3.hw,
2988 &g12a_fclk_div5.hw,
2989 &g12a_fclk_div7.hw,
2990 &g12a_mpll1.hw,
2991 &g12a_vid_pll.hw,
2992 &g12a_mpll2.hw,
2993 &g12a_fclk_div2p5.hw,
3002 .hw.init = &(struct clk_init_data){
3017 .hw.init = &(struct clk_init_data){
3021 &g12a_vapb_0_sel.hw
3033 .hw.init = &(struct clk_init_data) {
3037 &g12a_vapb_0_div.hw
3050 .hw.init = &(struct clk_init_data){
3065 .hw.init = &(struct clk_init_data){
3069 &g12a_vapb_1_sel.hw
3081 .hw.init = &(struct clk_init_data) {
3085 &g12a_vapb_1_div.hw
3098 .hw.init = &(struct clk_init_data){
3106 &g12a_vapb_0.hw,
3107 &g12a_vapb_1.hw,
3119 .hw.init = &(struct clk_init_data) {
3122 .parent_hws = (const struct clk_hw *[]) { &g12a_vapb_sel.hw },
3129 &g12a_vid_pll.hw,
3130 &g12a_gp0_pll.hw,
3131 &g12a_hifi_pll.hw,
3132 &g12a_mpll1.hw,
3133 &g12a_fclk_div3.hw,
3134 &g12a_fclk_div4.hw,
3135 &g12a_fclk_div5.hw,
3136 &g12a_fclk_div7.hw,
3145 .hw.init = &(struct clk_init_data){
3160 .hw.init = &(struct clk_init_data){
3174 .hw.init = &(struct clk_init_data) {
3177 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk_sel.hw },
3188 .hw.init = &(struct clk_init_data) {
3191 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_sel.hw },
3203 .hw.init = &(struct clk_init_data){
3207 &g12a_vclk_input.hw
3220 .hw.init = &(struct clk_init_data){
3224 &g12a_vclk2_input.hw
3236 .hw.init = &(struct clk_init_data) {
3239 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk_div.hw },
3250 .hw.init = &(struct clk_init_data) {
3253 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_div.hw },
3264 .hw.init = &(struct clk_init_data) {
3267 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3278 .hw.init = &(struct clk_init_data) {
3281 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3292 .hw.init = &(struct clk_init_data) {
3295 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3306 .hw.init = &(struct clk_init_data) {
3309 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3320 .hw.init = &(struct clk_init_data) {
3323 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3334 .hw.init = &(struct clk_init_data) {
3337 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3348 .hw.init = &(struct clk_init_data) {
3351 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3362 .hw.init = &(struct clk_init_data) {
3365 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3376 .hw.init = &(struct clk_init_data) {
3379 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3390 .hw.init = &(struct clk_init_data) {
3393 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3402 .hw.init = &(struct clk_init_data){
3406 &g12a_vclk_div2_en.hw
3415 .hw.init = &(struct clk_init_data){
3419 &g12a_vclk_div4_en.hw
3428 .hw.init = &(struct clk_init_data){
3432 &g12a_vclk_div6_en.hw
3441 .hw.init = &(struct clk_init_data){
3445 &g12a_vclk_div12_en.hw
3454 .hw.init = &(struct clk_init_data){
3458 &g12a_vclk2_div2_en.hw
3467 .hw.init = &(struct clk_init_data){
3471 &g12a_vclk2_div4_en.hw
3480 .hw.init = &(struct clk_init_data){
3484 &g12a_vclk2_div6_en.hw
3493 .hw.init = &(struct clk_init_data){
3497 &g12a_vclk2_div12_en.hw
3505 &g12a_vclk_div1.hw,
3506 &g12a_vclk_div2.hw,
3507 &g12a_vclk_div4.hw,
3508 &g12a_vclk_div6.hw,
3509 &g12a_vclk_div12.hw,
3510 &g12a_vclk2_div1.hw,
3511 &g12a_vclk2_div2.hw,
3512 &g12a_vclk2_div4.hw,
3513 &g12a_vclk2_div6.hw,
3514 &g12a_vclk2_div12.hw,
3524 .hw.init = &(struct clk_init_data){
3540 .hw.init = &(struct clk_init_data){
3556 .hw.init = &(struct clk_init_data){
3568 &g12a_vclk_div1.hw,
3569 &g12a_vclk_div2.hw,
3570 &g12a_vclk_div4.hw,
3571 &g12a_vclk_div6.hw,
3572 &g12a_vclk_div12.hw,
3573 &g12a_vclk2_div1.hw,
3574 &g12a_vclk2_div2.hw,
3575 &g12a_vclk2_div4.hw,
3576 &g12a_vclk2_div6.hw,
3577 &g12a_vclk2_div12.hw,
3587 .hw.init = &(struct clk_init_data){
3601 .hw.init = &(struct clk_init_data) {
3605 &g12a_cts_enci_sel.hw
3617 .hw.init = &(struct clk_init_data) {
3621 &g12a_cts_encp_sel.hw
3633 .hw.init = &(struct clk_init_data) {
3637 &g12a_cts_vdac_sel.hw
3649 .hw.init = &(struct clk_init_data) {
3653 &g12a_hdmi_tx_sel.hw
3664 { .hw = &g12a_fclk_div4.hw },
3665 { .hw = &g12a_fclk_div3.hw },
3666 { .hw = &g12a_fclk_div5.hw },
3676 .hw.init = &(struct clk_init_data){
3691 .hw.init = &(struct clk_init_data){
3694 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_sel.hw },
3705 .hw.init = &(struct clk_init_data) {
3708 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_div.hw },
3722 { .hw = &g12a_gp0_pll.hw },
3723 { .hw = &g12a_hifi_pll.hw },
3724 { .hw = &g12a_fclk_div2p5.hw },
3725 { .hw = &g12a_fclk_div3.hw },
3726 { .hw = &g12a_fclk_div4.hw },
3727 { .hw = &g12a_fclk_div5.hw },
3728 { .hw = &g12a_fclk_div7.hw },
3737 .hw.init = &(struct clk_init_data){
3758 .hw.init = &(struct clk_init_data){
3762 &g12a_mali_0_sel.hw
3774 .hw.init = &(struct clk_init_data){
3778 &g12a_mali_0_div.hw
3791 .hw.init = &(struct clk_init_data){
3812 .hw.init = &(struct clk_init_data){
3816 &g12a_mali_1_sel.hw
3828 .hw.init = &(struct clk_init_data){
3832 &g12a_mali_1_div.hw
3840 &g12a_mali_0.hw,
3841 &g12a_mali_1.hw,
3850 .hw.init = &(struct clk_init_data){
3865 .hw.init = &(struct clk_init_data){
3880 .hw.init = &(struct clk_init_data){
3884 &g12a_ts_div.hw
3894 { .hw = &g12a_clk81.hw },
3895 { .hw = &g12a_fclk_div4.hw },
3896 { .hw = &g12a_fclk_div3.hw },
3897 { .hw = &g12a_fclk_div5.hw },
3898 { .hw = &g12a_fclk_div7.hw },
3907 .hw.init = &(struct clk_init_data){
3921 .hw.init = &(struct clk_init_data){
3925 &g12a_spicc0_sclk_sel.hw
3937 .hw.init = &(struct clk_init_data){
3941 &g12a_spicc0_sclk_div.hw
3954 .hw.init = &(struct clk_init_data){
3968 .hw.init = &(struct clk_init_data){
3972 &g12a_spicc1_sclk_sel.hw
3984 .hw.init = &(struct clk_init_data){
3988 &g12a_spicc1_sclk_div.hw
3999 { .hw = &g12a_gp0_pll.hw, },
4000 { .hw = &g12a_hifi_pll.hw, },
4001 { .hw = &g12a_fclk_div2p5.hw, },
4002 { .hw = &g12a_fclk_div3.hw, },
4003 { .hw = &g12a_fclk_div4.hw, },
4004 { .hw = &g12a_fclk_div5.hw, },
4005 { .hw = &g12a_fclk_div7.hw },
4014 .hw.init = &(struct clk_init_data){
4028 .hw.init = &(struct clk_init_data){
4032 &sm1_nna_axi_clk_sel.hw
4044 .hw.init = &(struct clk_init_data){
4048 &sm1_nna_axi_clk_div.hw
4061 .hw.init = &(struct clk_init_data){
4075 .hw.init = &(struct clk_init_data){
4079 &sm1_nna_core_clk_sel.hw
4091 .hw.init = &(struct clk_init_data){
4095 &sm1_nna_core_clk_div.hw
4103 MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw)
4106 MESON_PCLK_RO(_name, _reg, _bit, &g12a_clk81.hw)
4186 [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
4187 [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
4188 [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
4189 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
4190 [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
4191 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
4192 [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
4193 [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
4194 [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
4195 [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
4196 [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
4197 [CLKID_CLK81] = &g12a_clk81.hw,
4198 [CLKID_MPLL0] = &g12a_mpll0.hw,
4199 [CLKID_MPLL1] = &g12a_mpll1.hw,
4200 [CLKID_MPLL2] = &g12a_mpll2.hw,
4201 [CLKID_MPLL3] = &g12a_mpll3.hw,
4202 [CLKID_DDR] = &g12a_ddr.hw,
4203 [CLKID_DOS] = &g12a_dos.hw,
4204 [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
4205 [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
4206 [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
4207 [CLKID_ISA] = &g12a_isa.hw,
4208 [CLKID_PL301] = &g12a_pl301.hw,
4209 [CLKID_PERIPHS] = &g12a_periphs.hw,
4210 [CLKID_SPICC0] = &g12a_spicc_0.hw,
4211 [CLKID_I2C] = &g12a_i2c.hw,
4212 [CLKID_SANA] = &g12a_sana.hw,
4213 [CLKID_SD] = &g12a_sd.hw,
4214 [CLKID_RNG0] = &g12a_rng0.hw,
4215 [CLKID_UART0] = &g12a_uart0.hw,
4216 [CLKID_SPICC1] = &g12a_spicc_1.hw,
4217 [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
4218 [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
4219 [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
4220 [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
4221 [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
4222 [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
4223 [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
4224 [CLKID_AUDIO] = &g12a_audio.hw,
4225 [CLKID_ETH] = &g12a_eth_core.hw,
4226 [CLKID_DEMUX] = &g12a_demux.hw,
4227 [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
4228 [CLKID_ADC] = &g12a_adc.hw,
4229 [CLKID_UART1] = &g12a_uart1.hw,
4230 [CLKID_G2D] = &g12a_g2d.hw,
4231 [CLKID_RESET] = &g12a_reset.hw,
4232 [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
4233 [CLKID_PARSER] = &g12a_parser.hw,
4234 [CLKID_USB] = &g12a_usb_general.hw,
4235 [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
4236 [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
4237 [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
4238 [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
4239 [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
4240 [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
4241 [CLKID_BT656] = &g12a_bt656.hw,
4242 [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
4243 [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
4244 [CLKID_UART2] = &g12a_uart2.hw,
4245 [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
4246 [CLKID_GIC] = &g12a_gic.hw,
4247 [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
4248 [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
4249 [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
4250 [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
4251 [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
4252 [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
4253 [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
4254 [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
4255 [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
4256 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
4257 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
4258 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
4259 [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
4260 [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
4261 [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
4262 [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
4263 [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
4264 [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
4265 [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
4266 [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
4267 [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
4268 [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
4269 [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
4270 [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
4271 [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
4272 [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
4273 [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
4274 [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
4275 [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
4276 [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
4277 [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
4278 [CLKID_IEC958] = &g12a_iec958_gate.hw,
4279 [CLKID_ENC480P] = &g12a_enc480p.hw,
4280 [CLKID_RNG1] = &g12a_rng1.hw,
4281 [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
4282 [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
4283 [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
4284 [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
4285 [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
4286 [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
4287 [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
4288 [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
4289 [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
4290 [CLKID_DMA] = &g12a_dma.hw,
4291 [CLKID_EFUSE] = &g12a_efuse.hw,
4292 [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
4293 [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
4294 [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
4295 [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
4296 [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
4297 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
4298 [CLKID_VPU_0] = &g12a_vpu_0.hw,
4299 [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
4300 [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
4301 [CLKID_VPU_1] = &g12a_vpu_1.hw,
4302 [CLKID_VPU] = &g12a_vpu.hw,
4303 [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
4304 [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
4305 [CLKID_VAPB_0] = &g12a_vapb_0.hw,
4306 [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
4307 [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
4308 [CLKID_VAPB_1] = &g12a_vapb_1.hw,
4309 [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
4310 [CLKID_VAPB] = &g12a_vapb.hw,
4311 [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
4312 [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
4313 [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
4314 [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
4315 [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
4316 [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
4317 [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
4318 [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
4319 [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
4320 [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
4321 [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
4322 [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
4323 [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
4324 [CLKID_VCLK] = &g12a_vclk.hw,
4325 [CLKID_VCLK2] = &g12a_vclk2.hw,
4326 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
4327 [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
4328 [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
4329 [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
4330 [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
4331 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
4332 [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
4333 [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
4334 [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
4335 [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
4336 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
4337 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
4338 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
4339 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
4340 [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
4341 [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
4342 [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
4343 [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
4344 [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
4345 [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
4346 [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
4347 [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
4348 [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
4349 [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
4350 [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
4351 [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
4352 [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
4353 [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
4354 [CLKID_HDMI] = &g12a_hdmi.hw,
4355 [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
4356 [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
4357 [CLKID_MALI_0] = &g12a_mali_0.hw,
4358 [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
4359 [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
4360 [CLKID_MALI_1] = &g12a_mali_1.hw,
4361 [CLKID_MALI] = &g12a_mali.hw,
4362 [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
4363 [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
4364 [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
4365 [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
4366 [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
4367 [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
4368 [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
4369 [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
4370 [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
4371 [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
4372 [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
4373 [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
4374 [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
4375 [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
4376 [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
4377 [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
4378 [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
4379 [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
4380 [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
4381 [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
4382 [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
4383 [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
4384 [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
4385 [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
4386 [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
4387 [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
4388 [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
4389 [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
4390 [CLKID_VDEC_1] = &g12a_vdec_1.hw,
4391 [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
4392 [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
4393 [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
4394 [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
4395 [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
4396 [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
4397 [CLKID_TS_DIV] = &g12a_ts_div.hw,
4398 [CLKID_TS] = &g12a_ts.hw,
4399 [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
4400 [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
4401 [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
4402 [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
4403 [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
4404 [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
4412 [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
4413 [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
4414 [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
4415 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
4416 [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
4417 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
4418 [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
4419 [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
4420 [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
4421 [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
4422 [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
4423 [CLKID_CLK81] = &g12a_clk81.hw,
4424 [CLKID_MPLL0] = &g12a_mpll0.hw,
4425 [CLKID_MPLL1] = &g12a_mpll1.hw,
4426 [CLKID_MPLL2] = &g12a_mpll2.hw,
4427 [CLKID_MPLL3] = &g12a_mpll3.hw,
4428 [CLKID_DDR] = &g12a_ddr.hw,
4429 [CLKID_DOS] = &g12a_dos.hw,
4430 [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
4431 [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
4432 [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
4433 [CLKID_ISA] = &g12a_isa.hw,
4434 [CLKID_PL301] = &g12a_pl301.hw,
4435 [CLKID_PERIPHS] = &g12a_periphs.hw,
4436 [CLKID_SPICC0] = &g12a_spicc_0.hw,
4437 [CLKID_I2C] = &g12a_i2c.hw,
4438 [CLKID_SANA] = &g12a_sana.hw,
4439 [CLKID_SD] = &g12a_sd.hw,
4440 [CLKID_RNG0] = &g12a_rng0.hw,
4441 [CLKID_UART0] = &g12a_uart0.hw,
4442 [CLKID_SPICC1] = &g12a_spicc_1.hw,
4443 [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
4444 [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
4445 [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
4446 [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
4447 [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
4448 [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
4449 [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
4450 [CLKID_AUDIO] = &g12a_audio.hw,
4451 [CLKID_ETH] = &g12a_eth_core.hw,
4452 [CLKID_DEMUX] = &g12a_demux.hw,
4453 [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
4454 [CLKID_ADC] = &g12a_adc.hw,
4455 [CLKID_UART1] = &g12a_uart1.hw,
4456 [CLKID_G2D] = &g12a_g2d.hw,
4457 [CLKID_RESET] = &g12a_reset.hw,
4458 [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
4459 [CLKID_PARSER] = &g12a_parser.hw,
4460 [CLKID_USB] = &g12a_usb_general.hw,
4461 [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
4462 [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
4463 [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
4464 [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
4465 [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
4466 [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
4467 [CLKID_BT656] = &g12a_bt656.hw,
4468 [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
4469 [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
4470 [CLKID_UART2] = &g12a_uart2.hw,
4471 [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
4472 [CLKID_GIC] = &g12a_gic.hw,
4473 [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
4474 [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
4475 [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
4476 [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
4477 [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
4478 [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
4479 [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
4480 [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
4481 [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
4482 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
4483 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
4484 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
4485 [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
4486 [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
4487 [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
4488 [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
4489 [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
4490 [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
4491 [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
4492 [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
4493 [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
4494 [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
4495 [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
4496 [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
4497 [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
4498 [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
4499 [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
4500 [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
4501 [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
4502 [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
4503 [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
4504 [CLKID_IEC958] = &g12a_iec958_gate.hw,
4505 [CLKID_ENC480P] = &g12a_enc480p.hw,
4506 [CLKID_RNG1] = &g12a_rng1.hw,
4507 [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
4508 [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
4509 [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
4510 [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
4511 [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
4512 [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
4513 [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
4514 [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
4515 [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
4516 [CLKID_DMA] = &g12a_dma.hw,
4517 [CLKID_EFUSE] = &g12a_efuse.hw,
4518 [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
4519 [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
4520 [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
4521 [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
4522 [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
4523 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
4524 [CLKID_VPU_0] = &g12a_vpu_0.hw,
4525 [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
4526 [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
4527 [CLKID_VPU_1] = &g12a_vpu_1.hw,
4528 [CLKID_VPU] = &g12a_vpu.hw,
4529 [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
4530 [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
4531 [CLKID_VAPB_0] = &g12a_vapb_0.hw,
4532 [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
4533 [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
4534 [CLKID_VAPB_1] = &g12a_vapb_1.hw,
4535 [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
4536 [CLKID_VAPB] = &g12a_vapb.hw,
4537 [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
4538 [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
4539 [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
4540 [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
4541 [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
4542 [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
4543 [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
4544 [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
4545 [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
4546 [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
4547 [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
4548 [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
4549 [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
4550 [CLKID_VCLK] = &g12a_vclk.hw,
4551 [CLKID_VCLK2] = &g12a_vclk2.hw,
4552 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
4553 [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
4554 [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
4555 [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
4556 [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
4557 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
4558 [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
4559 [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
4560 [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
4561 [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
4562 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
4563 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
4564 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
4565 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
4566 [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
4567 [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
4568 [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
4569 [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
4570 [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
4571 [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
4572 [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
4573 [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
4574 [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
4575 [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
4576 [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
4577 [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
4578 [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
4579 [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
4580 [CLKID_HDMI] = &g12a_hdmi.hw,
4581 [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
4582 [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
4583 [CLKID_MALI_0] = &g12a_mali_0.hw,
4584 [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
4585 [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
4586 [CLKID_MALI_1] = &g12a_mali_1.hw,
4587 [CLKID_MALI] = &g12a_mali.hw,
4588 [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
4589 [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
4590 [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
4591 [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
4592 [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
4593 [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
4594 [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
4595 [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
4596 [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
4597 [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
4598 [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
4599 [CLKID_CPU_CLK] = &g12b_cpu_clk.hw,
4600 [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
4601 [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
4602 [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
4603 [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
4604 [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
4605 [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
4606 [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
4607 [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
4608 [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
4609 [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
4610 [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
4611 [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
4612 [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
4613 [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
4614 [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
4615 [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
4616 [CLKID_VDEC_1] = &g12a_vdec_1.hw,
4617 [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
4618 [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
4619 [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
4620 [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
4621 [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
4622 [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
4623 [CLKID_TS_DIV] = &g12a_ts_div.hw,
4624 [CLKID_TS] = &g12a_ts.hw,
4625 [CLKID_SYS1_PLL_DCO] = &g12b_sys1_pll_dco.hw,
4626 [CLKID_SYS1_PLL] = &g12b_sys1_pll.hw,
4627 [CLKID_SYS1_PLL_DIV16_EN] = &g12b_sys1_pll_div16_en.hw,
4628 [CLKID_SYS1_PLL_DIV16] = &g12b_sys1_pll_div16.hw,
4629 [CLKID_CPUB_CLK_DYN0_SEL] = &g12b_cpub_clk_premux0.hw,
4630 [CLKID_CPUB_CLK_DYN0_DIV] = &g12b_cpub_clk_mux0_div.hw,
4631 [CLKID_CPUB_CLK_DYN0] = &g12b_cpub_clk_postmux0.hw,
4632 [CLKID_CPUB_CLK_DYN1_SEL] = &g12b_cpub_clk_premux1.hw,
4633 [CLKID_CPUB_CLK_DYN1_DIV] = &g12b_cpub_clk_mux1_div.hw,
4634 [CLKID_CPUB_CLK_DYN1] = &g12b_cpub_clk_postmux1.hw,
4635 [CLKID_CPUB_CLK_DYN] = &g12b_cpub_clk_dyn.hw,
4636 [CLKID_CPUB_CLK] = &g12b_cpub_clk.hw,
4637 [CLKID_CPUB_CLK_DIV16_EN] = &g12b_cpub_clk_div16_en.hw,
4638 [CLKID_CPUB_CLK_DIV16] = &g12b_cpub_clk_div16.hw,
4639 [CLKID_CPUB_CLK_DIV2] = &g12b_cpub_clk_div2.hw,
4640 [CLKID_CPUB_CLK_DIV3] = &g12b_cpub_clk_div3.hw,
4641 [CLKID_CPUB_CLK_DIV4] = &g12b_cpub_clk_div4.hw,
4642 [CLKID_CPUB_CLK_DIV5] = &g12b_cpub_clk_div5.hw,
4643 [CLKID_CPUB_CLK_DIV6] = &g12b_cpub_clk_div6.hw,
4644 [CLKID_CPUB_CLK_DIV7] = &g12b_cpub_clk_div7.hw,
4645 [CLKID_CPUB_CLK_DIV8] = &g12b_cpub_clk_div8.hw,
4646 [CLKID_CPUB_CLK_APB_SEL] = &g12b_cpub_clk_apb_sel.hw,
4647 [CLKID_CPUB_CLK_APB] = &g12b_cpub_clk_apb.hw,
4648 [CLKID_CPUB_CLK_ATB_SEL] = &g12b_cpub_clk_atb_sel.hw,
4649 [CLKID_CPUB_CLK_ATB] = &g12b_cpub_clk_atb.hw,
4650 [CLKID_CPUB_CLK_AXI_SEL] = &g12b_cpub_clk_axi_sel.hw,
4651 [CLKID_CPUB_CLK_AXI] = &g12b_cpub_clk_axi.hw,
4652 [CLKID_CPUB_CLK_TRACE_SEL] = &g12b_cpub_clk_trace_sel.hw,
4653 [CLKID_CPUB_CLK_TRACE] = &g12b_cpub_clk_trace.hw,
4654 [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
4655 [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
4656 [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
4657 [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
4658 [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
4659 [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
4667 [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
4668 [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
4669 [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
4670 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
4671 [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
4672 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
4673 [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
4674 [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
4675 [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
4676 [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
4677 [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
4678 [CLKID_CLK81] = &g12a_clk81.hw,
4679 [CLKID_MPLL0] = &g12a_mpll0.hw,
4680 [CLKID_MPLL1] = &g12a_mpll1.hw,
4681 [CLKID_MPLL2] = &g12a_mpll2.hw,
4682 [CLKID_MPLL3] = &g12a_mpll3.hw,
4683 [CLKID_DDR] = &g12a_ddr.hw,
4684 [CLKID_DOS] = &g12a_dos.hw,
4685 [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
4686 [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
4687 [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
4688 [CLKID_ISA] = &g12a_isa.hw,
4689 [CLKID_PL301] = &g12a_pl301.hw,
4690 [CLKID_PERIPHS] = &g12a_periphs.hw,
4691 [CLKID_SPICC0] = &g12a_spicc_0.hw,
4692 [CLKID_I2C] = &g12a_i2c.hw,
4693 [CLKID_SANA] = &g12a_sana.hw,
4694 [CLKID_SD] = &g12a_sd.hw,
4695 [CLKID_RNG0] = &g12a_rng0.hw,
4696 [CLKID_UART0] = &g12a_uart0.hw,
4697 [CLKID_SPICC1] = &g12a_spicc_1.hw,
4698 [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
4699 [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
4700 [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
4701 [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
4702 [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
4703 [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
4704 [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
4705 [CLKID_AUDIO] = &g12a_audio.hw,
4706 [CLKID_ETH] = &g12a_eth_core.hw,
4707 [CLKID_DEMUX] = &g12a_demux.hw,
4708 [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
4709 [CLKID_ADC] = &g12a_adc.hw,
4710 [CLKID_UART1] = &g12a_uart1.hw,
4711 [CLKID_G2D] = &g12a_g2d.hw,
4712 [CLKID_RESET] = &g12a_reset.hw,
4713 [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
4714 [CLKID_PARSER] = &g12a_parser.hw,
4715 [CLKID_USB] = &g12a_usb_general.hw,
4716 [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
4717 [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
4718 [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
4719 [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
4720 [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
4721 [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
4722 [CLKID_BT656] = &g12a_bt656.hw,
4723 [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
4724 [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
4725 [CLKID_UART2] = &g12a_uart2.hw,
4726 [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
4727 [CLKID_GIC] = &g12a_gic.hw,
4728 [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
4729 [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
4730 [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
4731 [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
4732 [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
4733 [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
4734 [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
4735 [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
4736 [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
4737 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
4738 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
4739 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
4740 [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
4741 [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
4742 [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
4743 [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
4744 [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
4745 [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
4746 [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
4747 [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
4748 [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
4749 [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
4750 [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
4751 [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
4752 [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
4753 [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
4754 [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
4755 [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
4756 [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
4757 [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
4758 [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
4759 [CLKID_IEC958] = &g12a_iec958_gate.hw,
4760 [CLKID_ENC480P] = &g12a_enc480p.hw,
4761 [CLKID_RNG1] = &g12a_rng1.hw,
4762 [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
4763 [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
4764 [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
4765 [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
4766 [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
4767 [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
4768 [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
4769 [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
4770 [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
4771 [CLKID_DMA] = &g12a_dma.hw,
4772 [CLKID_EFUSE] = &g12a_efuse.hw,
4773 [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
4774 [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
4775 [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
4776 [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
4777 [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
4778 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
4779 [CLKID_VPU_0] = &g12a_vpu_0.hw,
4780 [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
4781 [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
4782 [CLKID_VPU_1] = &g12a_vpu_1.hw,
4783 [CLKID_VPU] = &g12a_vpu.hw,
4784 [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
4785 [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
4786 [CLKID_VAPB_0] = &g12a_vapb_0.hw,
4787 [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
4788 [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
4789 [CLKID_VAPB_1] = &g12a_vapb_1.hw,
4790 [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
4791 [CLKID_VAPB] = &g12a_vapb.hw,
4792 [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
4793 [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
4794 [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
4795 [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
4796 [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
4797 [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
4798 [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
4799 [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
4800 [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
4801 [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
4802 [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
4803 [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
4804 [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
4805 [CLKID_VCLK] = &g12a_vclk.hw,
4806 [CLKID_VCLK2] = &g12a_vclk2.hw,
4807 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
4808 [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
4809 [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
4810 [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
4811 [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
4812 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
4813 [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
4814 [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
4815 [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
4816 [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
4817 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
4818 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
4819 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
4820 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
4821 [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
4822 [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
4823 [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
4824 [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
4825 [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
4826 [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
4827 [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
4828 [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
4829 [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
4830 [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
4831 [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
4832 [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
4833 [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
4834 [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
4835 [CLKID_HDMI] = &g12a_hdmi.hw,
4836 [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
4837 [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
4838 [CLKID_MALI_0] = &g12a_mali_0.hw,
4839 [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
4840 [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
4841 [CLKID_MALI_1] = &g12a_mali_1.hw,
4842 [CLKID_MALI] = &g12a_mali.hw,
4843 [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
4844 [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
4845 [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
4846 [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
4847 [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
4848 [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
4849 [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
4850 [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
4851 [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
4852 [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
4853 [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
4854 [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
4855 [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
4856 [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
4857 [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
4858 [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
4859 [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
4860 [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
4861 [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
4862 [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
4863 [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
4864 [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
4865 [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
4866 [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
4867 [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
4868 [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
4869 [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
4870 [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
4871 [CLKID_VDEC_1] = &g12a_vdec_1.hw,
4872 [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
4873 [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
4874 [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
4875 [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
4876 [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
4877 [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
4878 [CLKID_TS_DIV] = &g12a_ts_div.hw,
4879 [CLKID_TS] = &g12a_ts.hw,
4880 [CLKID_GP1_PLL_DCO] = &sm1_gp1_pll_dco.hw,
4881 [CLKID_GP1_PLL] = &sm1_gp1_pll.hw,
4882 [CLKID_DSU_CLK_DYN0_SEL] = &sm1_dsu_clk_premux0.hw,
4883 [CLKID_DSU_CLK_DYN0_DIV] = &sm1_dsu_clk_premux1.hw,
4884 [CLKID_DSU_CLK_DYN0] = &sm1_dsu_clk_mux0_div.hw,
4885 [CLKID_DSU_CLK_DYN1_SEL] = &sm1_dsu_clk_postmux0.hw,
4886 [CLKID_DSU_CLK_DYN1_DIV] = &sm1_dsu_clk_mux1_div.hw,
4887 [CLKID_DSU_CLK_DYN1] = &sm1_dsu_clk_postmux1.hw,
4888 [CLKID_DSU_CLK_DYN] = &sm1_dsu_clk_dyn.hw,
4889 [CLKID_DSU_CLK_FINAL] = &sm1_dsu_final_clk.hw,
4890 [CLKID_DSU_CLK] = &sm1_dsu_clk.hw,
4891 [CLKID_CPU1_CLK] = &sm1_cpu1_clk.hw,
4892 [CLKID_CPU2_CLK] = &sm1_cpu2_clk.hw,
4893 [CLKID_CPU3_CLK] = &sm1_cpu3_clk.hw,
4894 [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
4895 [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
4896 [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
4897 [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
4898 [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
4899 [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
4900 [CLKID_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw,
4901 [CLKID_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw,
4902 [CLKID_NNA_AXI_CLK] = &sm1_nna_axi_clk.hw,
4903 [CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw,
4904 [CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw,
4905 [CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw,
5171 notifier_clk_name = clk_hw_get_name(&g12a_cpu_clk_postmux0.hw); in meson_g12a_dvfs_setup_common()
5181 notifier_clk_name = clk_hw_get_name(&g12a_cpu_clk_dyn.hw); in meson_g12a_dvfs_setup_common()
5207 notifier_clk_name = clk_hw_get_name(&g12b_cpu_clk.hw); in meson_g12b_dvfs_setup()
5216 notifier_clk_name = clk_hw_get_name(&g12b_sys1_pll.hw); in meson_g12b_dvfs_setup()
5229 notifier_clk_name = clk_hw_get_name(&g12b_cpub_clk_postmux0.hw); in meson_g12b_dvfs_setup()
5239 notifier_clk_name = clk_hw_get_name(&g12b_cpub_clk_dyn.hw); in meson_g12b_dvfs_setup()
5248 notifier_clk_name = clk_hw_get_name(&g12b_cpub_clk.hw); in meson_g12b_dvfs_setup()
5257 notifier_clk_name = clk_hw_get_name(&g12a_sys_pll.hw); in meson_g12b_dvfs_setup()
5281 notifier_clk_name = clk_hw_get_name(&g12a_cpu_clk.hw); in meson_g12a_dvfs_setup()
5290 notifier_clk_name = clk_hw_get_name(&g12a_sys_pll.hw); in meson_g12a_dvfs_setup()