clk/mediatek/clk-mt7622.c

295 	.set_ofs = 0x8,
296 	.clr_ofs = 0x8,
297 	.sta_ofs = 0x8,
301 	.set_ofs = 0x40,
302 	.clr_ofs = 0x44,
303 	.sta_ofs = 0x48,
307 	.set_ofs = 0x120,
308 	.clr_ofs = 0x120,
309 	.sta_ofs = 0x120,
313 	.set_ofs = 0x128,
314 	.clr_ofs = 0x128,
315 	.sta_ofs = 0x128,
319 	.set_ofs = 0x8,
320 	.clr_ofs = 0x10,
321 	.sta_ofs = 0x18,
325 	.set_ofs = 0xC,
326 	.clr_ofs = 0x14,
327 	.sta_ofs = 0x1C,
331 	PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001,
332 	    PLL_AO, 21, 0x0204, 24, 0, 0x0204, 0),
333 	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0x00000001,
334 	    HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0),
335 	PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0x00000001,
336 	    HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14),
337 	PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0x00000001,
338 	    0, 21, 0x0300, 1, 0, 0x0304, 0),
339 	PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0x00000001,
340 	    0, 21, 0x0314, 1, 0, 0x0318, 0),
341 	PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x0324, 0x0330, 0x00000001,
342 	    0, 31, 0x0324, 1, 0, 0x0328, 0),
343 	PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x0334, 0x0340, 0x00000001,
344 	    0, 31, 0x0334, 1, 0, 0x0338, 0),
345 	PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x0344, 0x0354, 0x00000001,
346 	    0, 21, 0x0344, 1, 0, 0x0348, 0),
347 	PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0x00000001,
348 	    0, 21, 0x0358, 1, 0, 0x035C, 0),
356 	GATE_INFRA(CLK_INFRA_DBGCLK_PD, "infra_dbgclk_pd", "axi_sel", 0),
438 	GATE_TOP0(CLK_TOP_APLL1_DIV_PD, "apll1_ck_div_pd", "apll1_ck_div", 0),
450 	GATE_TOP1(CLK_TOP_A1SYS_HP_DIV_PD, "a1sys_div_pd", "a1sys_div", 0),
456 		0x120, 24, 3),
458 		0x120, 28, 3),
460 		0x124, 0, 7),
462 		0x124, 8, 7),
464 		0x124, 16, 7),
466 		0x124, 24, 7),
468 		0x128, 8, 7),
470 		0x128, 24, 7),
510 	    0x000, 2, 2),
516 		 0x040, 0, 3, 7),
518 		 0x040, 8, 1, 15),
520 		 0x040, 16, 1, 23),
522 		 0x040, 24, 3, 31),
526 		 0x050, 0, 2, 7),
528 		 0x050, 8, 1, 15),
530 		 0x050, 16, 4, 23),
532 		 0x050, 24, 3, 31),
536 		 0x060, 0, 1, 7),
538 		 0x060, 8, 3, 15),
540 		 0x060, 16, 3, 23),
542 		 0x060, 24, 3, 31),
546 		 0x070, 0, 3, 7),
548 		 0x070, 8, 3, 15),
550 		 0x070, 16, 2, 23),
552 		 0x070, 24, 2, 31),
556 		 0x080, 0, 2, 7),
558 		 0x080, 8, 2, 15),
560 		 0x080, 16, 3, 23),
562 		 0x080, 24, 2, 31),
566 		 0x090, 0, 2, 7),
568 		 0x090, 8, 3, 15),
570 		 0x090, 16, 2, 23),
572 		 0x090, 24, 2, 31),
576 		 0x0A0, 0, 1, 7),
578 		 0x0A0, 8, 1, 15),
580 		 0x0A0, 16, 1, 23),
582 		 0x0A0, 24, 1, 31),
586 		 0x0B0, 0, 2, 7),
588 		 0x0B0, 8, 2, 15),
590 		 0x0B0, 16, 2, 23),
594 	    0x120, 6, 1),
596 	    0x120, 7, 1),
598 	    0x120, 8, 1),
600 	    0x120, 9, 1),
602 	    0x120, 10, 1),
604 	    0x120, 11, 1),
609 	MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1),
618 	base = devm_platform_ioremap_resource(pdev, 0);  in mtk_topckgen_init()
665 	mtk_register_reset_controller(node, 1, 0x30);  in mtk_infrasys_init()
667 	return 0;  in mtk_infrasys_init()
698 	base = devm_platform_ioremap_resource(pdev, 0);  in mtk_pericfg_init()
716 	mtk_register_reset_controller(node, 2, 0x0);  in mtk_pericfg_init()
718 	return 0;  in mtk_pericfg_init()