clk/imx/clk-imx6sl.c

1 // SPDX-License-Identifier: GPL-2.0-only
3  * Copyright 2013-2014 Freescale Semiconductor, Inc.
13 #include <dt-bindings/clock/imx6sl-clock.h>
105  * ERR005311 CCM: After exit from WAIT mode, unwanted interrupt(s) taken
122  * 396MHz   ->   132MHz;
123  * 792MHz   ->   158.4MHz;
124  * 996MHz   ->   142.3MHz;
200 	clk_hw_data->num = IMX6SL_CLK_END;  in imx6sl_clocks_init()
201 	hws = clk_hw_data->hws;  in imx6sl_clocks_init()
209 	np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-anatop");  in imx6sl_clocks_init()
241 	clk_set_parent(hws[IMX6SL_PLL1_BYPASS]->clk, hws[IMX6SL_CLK_PLL1]->clk);  in imx6sl_clocks_init()
242 	clk_set_parent(hws[IMX6SL_PLL2_BYPASS]->clk, hws[IMX6SL_CLK_PLL2]->clk);  in imx6sl_clocks_init()
243 	clk_set_parent(hws[IMX6SL_PLL3_BYPASS]->clk, hws[IMX6SL_CLK_PLL3]->clk);  in imx6sl_clocks_init()
244 	clk_set_parent(hws[IMX6SL_PLL4_BYPASS]->clk, hws[IMX6SL_CLK_PLL4]->clk);  in imx6sl_clocks_init()
245 	clk_set_parent(hws[IMX6SL_PLL5_BYPASS]->clk, hws[IMX6SL_CLK_PLL5]->clk);  in imx6sl_clocks_init()
246 	clk_set_parent(hws[IMX6SL_PLL6_BYPASS]->clk, hws[IMX6SL_CLK_PLL6]->clk);  in imx6sl_clocks_init()
247 	clk_set_parent(hws[IMX6SL_PLL7_BYPASS]->clk, hws[IMX6SL_CLK_PLL7]->clk);  in imx6sl_clocks_init()
430 	ret = clk_set_rate(hws[IMX6SL_CLK_AHB]->clk, 132000000);  in imx6sl_clocks_init()
436 		clk_prepare_enable(hws[IMX6SL_CLK_USBPHY1_GATE]->clk);  in imx6sl_clocks_init()
437 		clk_prepare_enable(hws[IMX6SL_CLK_USBPHY2_GATE]->clk);  in imx6sl_clocks_init()
440 	/* Audio-related clocks configuration */  in imx6sl_clocks_init()
441 	clk_set_parent(hws[IMX6SL_CLK_SPDIF0_SEL]->clk, hws[IMX6SL_CLK_PLL3_PFD3]->clk);  in imx6sl_clocks_init()
444 	clk_set_parent(hws[IMX6SL_CLK_LCDIF_PIX_SEL]->clk,  in imx6sl_clocks_init()
445 			hws[IMX6SL_CLK_PLL5_VIDEO_DIV]->clk);  in imx6sl_clocks_init()
447 	clk_set_parent(hws[IMX6SL_CLK_LCDIF_AXI_SEL]->clk,  in imx6sl_clocks_init()
448 		       hws[IMX6SL_CLK_PLL2_PFD2]->clk);  in imx6sl_clocks_init()
453 		uart_clks[i] = &hws[index]->clk;  in imx6sl_clocks_init()
458 CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init);