1 // SPDX-License-Identifier: GPL-2.0-or-later
3  * Copyright 2011-2013 Freescale Semiconductor, Inc.
12 #include <linux/clk-provider.h>
19 #include <dt-bindings/clock/imx6qdl-clock.h>
130 	return of_machine_is_compatible("fsl,imx6q");  in clk_on_imx6q()
156 			return -ENOENT;  in ldb_di_sel_by_clock_id()
167 		return -ENOENT;  in ldb_di_sel_by_clock_id()
179 	num_parents = of_count_phandle_with_args(node, "assigned-clock-parents",  in of_assigned_ldb_sels()
180 						 "#clock-cells");  in of_assigned_ldb_sels()
182 		rc = of_parse_phandle_with_args(node, "assigned-clock-parents",  in of_assigned_ldb_sels()
183 					"#clock-cells", index, &clkspec);  in of_assigned_ldb_sels()
186 			if (rc == -ENOENT)  in of_assigned_ldb_sels()
197 		rc = of_parse_phandle_with_args(node, "assigned-clocks",  in of_assigned_ldb_sels()
198 				"#clock-cells", index, &clkspec);  in of_assigned_ldb_sels()
230 	num_clocks = of_count_phandle_with_args(node, "assigned-clocks",  in pll6_bypassed()
231 						"#clock-cells");  in pll6_bypassed()
236 		ret = of_parse_phandle_with_args(node, "assigned-clocks",  in pll6_bypassed()
237 						 "#clock-cells", index,  in pll6_bypassed()
251 	ret = of_parse_phandle_with_args(node, "assigned-clock-parents",  in pll6_bypassed()
252 					 "#clock-cells", index, &clkspec);  in pll6_bypassed()
277 	clk_set_parent(hws[IMX6QDL_CLK_PERIPH2_CLK2_SEL]->clk,  in mmdc_ch1_disable()
278 		       hws[IMX6QDL_CLK_PLL3_USB_OTG]->clk);  in mmdc_ch1_disable()
308  *    to decide between the first and second 4-port mux:
310  *    pll5_video_div 0 --|\
311  *    pll2_pfd0_352m 1 --| |_
312  *    pll2_pfd2_396m 2 --| | `-|\
313  *    mmdc_ch1_axi   3 --|/    | |
314  *                             | |--
315  *    pll3_usb_otg   4 --|\    | |
316  *                   5 --| |_,-|/
317  *                   6 --| |
318  *                   7 --|/
320  * The ldb_di0/1_clk_sel[1:0] bits control both 4-port muxes at the same time.
321  * The ldb_di0/1_clk_sel[2] bit controls the 2-port mux. The code below
352 		    (clk_get_parent(hws[IMX6QDL_CLK_PERIPH_PRE]->clk) ==  in init_ldb_clks()
353 		     hws[IMX6QDL_CLK_PLL2_PFD2_396M]->clk)) {  in init_ldb_clks()
366 		pr_debug("ccm: switching ldb_di%d_sel: %d->%d->%d->%d\n", i,  in init_ldb_clks()
402 	/* Make sure PLL2 PFDs 0-2 are gated */  in disable_anatop_clocks()
404 	/* Cannot gate PFD2 if pll2_pfd2_396m is the parent of MMDC clock */  in disable_anatop_clocks()
405 	if (clk_get_parent(hws[IMX6QDL_CLK_PERIPH_PRE]->clk) ==  in disable_anatop_clocks()
406 	    hws[IMX6QDL_CLK_PLL2_PFD2_396M]->clk)  in disable_anatop_clocks()
412 	/* Make sure PLL3 PFDs 0-3 are gated */  in disable_anatop_clocks()
450 	clk_hw_data->num = IMX6QDL_CLK_END;  in imx6q_clocks_init()
451 	hws = clk_hw_data->hws;  in imx6q_clocks_init()
463 	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");  in imx6q_clocks_init()
502 	clk_set_parent(hws[IMX6QDL_PLL1_BYPASS]->clk, hws[IMX6QDL_CLK_PLL1]->clk);  in imx6q_clocks_init()
503 	clk_set_parent(hws[IMX6QDL_PLL2_BYPASS]->clk, hws[IMX6QDL_CLK_PLL2]->clk);  in imx6q_clocks_init()
504 	clk_set_parent(hws[IMX6QDL_PLL3_BYPASS]->clk, hws[IMX6QDL_CLK_PLL3]->clk);  in imx6q_clocks_init()
505 	clk_set_parent(hws[IMX6QDL_PLL4_BYPASS]->clk, hws[IMX6QDL_CLK_PLL4]->clk);  in imx6q_clocks_init()
506 	clk_set_parent(hws[IMX6QDL_PLL5_BYPASS]->clk, hws[IMX6QDL_CLK_PLL5]->clk);  in imx6q_clocks_init()
507 	clk_set_parent(hws[IMX6QDL_PLL6_BYPASS]->clk, hws[IMX6QDL_CLK_PLL6]->clk);  in imx6q_clocks_init()
508 	clk_set_parent(hws[IMX6QDL_PLL7_BYPASS]->clk, hws[IMX6QDL_CLK_PLL7]->clk);  in imx6q_clocks_init()
519 	 * Bit 20 is the reserved and read-only bit, we do this only for:  in imx6q_clocks_init()
520 	 * - Do nothing for usbphy clk_enable/disable  in imx6q_clocks_init()
521 	 * - Keep refcount when do usbphy clk_enable/disable, in that case,  in imx6q_clocks_init()
536 	 * different post-dividers that are all affected by the single bypass  in imx6q_clocks_init()
564 	 * lvds1_gate and lvds2_gate are pseudo-gates.  Both can be  in imx6q_clocks_init()
656 		 * The LDB_DI0/1_SEL muxes are registered read-only due to a hardware  in imx6q_clocks_init()
856 		 * The multiplexer and divider of the imx6q clock gpu2d get  in imx6q_clocks_init()
925 	clk_set_rate(hws[IMX6QDL_CLK_PLL3_PFD1_540M]->clk, 540000000);  in imx6q_clocks_init()
927 		clk_set_parent(hws[IMX6QDL_CLK_IPU1_SEL]->clk, hws[IMX6QDL_CLK_PLL3_PFD1_540M]->clk);  in imx6q_clocks_init()
929 	clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI0_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk);  in imx6q_clocks_init()
930 	clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI1_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk);  in imx6q_clocks_init()
931 	clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI0_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk);  in imx6q_clocks_init()
932 	clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI1_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk);  in imx6q_clocks_init()
933 	clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI0_SEL]->clk, hws[IMX6QDL_CLK_IPU1_DI0_PRE]->clk);  in imx6q_clocks_init()
934 	clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI1_SEL]->clk, hws[IMX6QDL_CLK_IPU1_DI1_PRE]->clk);  in imx6q_clocks_init()
935 	clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI0_SEL]->clk, hws[IMX6QDL_CLK_IPU2_DI0_PRE]->clk);  in imx6q_clocks_init()
936 	clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI1_SEL]->clk, hws[IMX6QDL_CLK_IPU2_DI1_PRE]->clk);  in imx6q_clocks_init()
943 	clk_set_parent(hws[IMX6QDL_CLK_ENFC_SEL]->clk, hws[IMX6QDL_CLK_PLL2_PFD2_396M]->clk);  in imx6q_clocks_init()
946 		clk_prepare_enable(hws[IMX6QDL_CLK_USBPHY1_GATE]->clk);  in imx6q_clocks_init()
947 		clk_prepare_enable(hws[IMX6QDL_CLK_USBPHY2_GATE]->clk);  in imx6q_clocks_init()
952 	 * is widely used by imx6q board designs to clock audio codec.  in imx6q_clocks_init()
954 	ret = clk_set_parent(hws[IMX6QDL_CLK_CKO2_SEL]->clk, hws[IMX6QDL_CLK_OSC]->clk);  in imx6q_clocks_init()
956 		ret = clk_set_parent(hws[IMX6QDL_CLK_CKO]->clk, hws[IMX6QDL_CLK_CKO2]->clk);  in imx6q_clocks_init()
960 	/* Audio-related clocks configuration */  in imx6q_clocks_init()
961 	clk_set_parent(hws[IMX6QDL_CLK_SPDIF_SEL]->clk, hws[IMX6QDL_CLK_PLL3_PFD3_454M]->clk);  in imx6q_clocks_init()
965 		clk_set_parent(hws[IMX6QDL_CLK_LVDS1_SEL]->clk, hws[IMX6QDL_CLK_SATA_REF_100M]->clk);  in imx6q_clocks_init()
972 		clk_set_parent(hws[IMX6QDL_CLK_GPU3D_CORE_SEL]->clk,  in imx6q_clocks_init()
973 			       hws[IMX6QDL_CLK_PLL2_PFD1_594M]->clk);  in imx6q_clocks_init()
974 		clk_set_parent(hws[IMX6QDL_CLK_GPU2D_CORE_SEL]->clk,  in imx6q_clocks_init()
975 			       hws[IMX6QDL_CLK_PLL2_PFD1_594M]->clk);  in imx6q_clocks_init()
977 		clk_set_parent(hws[IMX6QDL_CLK_GPU3D_CORE_SEL]->clk,  in imx6q_clocks_init()
978 			       hws[IMX6QDL_CLK_MMDC_CH0_AXI]->clk);  in imx6q_clocks_init()
979 		clk_set_parent(hws[IMX6QDL_CLK_GPU3D_SHADER_SEL]->clk,  in imx6q_clocks_init()
980 			       hws[IMX6QDL_CLK_PLL2_PFD1_594M]->clk);  in imx6q_clocks_init()
981 		clk_set_parent(hws[IMX6QDL_CLK_GPU2D_CORE_SEL]->clk,  in imx6q_clocks_init()
982 			       hws[IMX6QDL_CLK_PLL3_USB_OTG]->clk);  in imx6q_clocks_init()
988 		uart_clks[i] = &hws[index]->clk;  in imx6q_clocks_init()
993 CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);