clk/imx/clk-imx35.c

18 #define MX35_CCM_BASE_ADDR	0x53f80000
19 #define MX35_GPT1_BASE_ADDR	0x53f90000
22 #define MXC_CCM_PDR0		0x04
23 #define MX35_CCM_PDR2		0x0c
24 #define MX35_CCM_PDR3		0x10
25 #define MX35_CCM_PDR4		0x14
26 #define MX35_CCM_MPCTL		0x1c
27 #define MX35_CCM_PPCTL		0x20
28 #define MX35_CCM_CGR0		0x2c
29 #define MX35_CCM_CGR1		0x30
30 #define MX35_CCM_CGR2		0x34
31 #define MX35_CCM_CGR3		0x38
38 	{ .arm = 1, .ahb = 4, .sel = 0},
40 	{ .arm = 2, .ahb = 2, .sel = 0},
41 	{ .arm = 0, .ahb = 0, .sel = 0},
42 	{ .arm = 0, .ahb = 0, .sel = 0},
43 	{ .arm = 0, .ahb = 0, .sel = 0},
44 	{ .arm = 4, .ahb = 1, .sel = 0},
45 	{ .arm = 1, .ahb = 5, .sel = 0},
46 	{ .arm = 1, .ahb = 8, .sel = 0},
48 	{ .arm = 2, .ahb = 4, .sel = 0},
49 	{ .arm = 0, .ahb = 0, .sel = 0},
50 	{ .arm = 0, .ahb = 0, .sel = 0},
51 	{ .arm = 0, .ahb = 0, .sel = 0},
52 	{ .arm = 4, .ahb = 2, .sel = 0},
53 	{ .arm = 0, .ahb = 0, .sel = 0},
56 static char hsp_div_532[] = { 4, 8, 3, 0 };
57 static char hsp_div_400[] = { 3, 6, 3, 0 };
65 	/*  0 */ ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb,
104 	consumer_sel = (pdr0 >> 16) & 0xf;  in _mx35_clocks_init()
107 		pr_err("i.MX35 clk: illegal consumer mux selection 0x%x\n", consumer_sel);  in _mx35_clocks_init()
112 		aad = &clk_consumer[0];  in _mx35_clocks_init()
132 	hsp_sel = (pdr0 >> 20) & 0x3;  in _mx35_clocks_init()
134 		pr_err("i.MX35 clk: illegal hsp clk selection 0x%x\n", hsp_sel);  in _mx35_clocks_init()
135 		hsp_sel = 0;  in _mx35_clocks_init()
151 	clk[esdhc1_div] = imx_clk_divider("esdhc1_div", "esdhc_sel", base + MX35_CCM_PDR3, 0, 6);  in _mx35_clocks_init()
161 	clk[ssi1_div_post] = imx_clk_divider("ssi1_div_post", "ssi1_div_pre", base + MX35_CCM_PDR2, 0, 6);  in _mx35_clocks_init()
173 	clk[asrc_gate] = imx_clk_gate2("asrc_gate", "ipg", base + MX35_CCM_CGR0,  0);  in _mx35_clocks_init()
190 	clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", base + MX35_CCM_CGR1,  0);  in _mx35_clocks_init()
207 	clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MX35_CCM_CGR2,  0);  in _mx35_clocks_init()
223 	clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MX35_CCM_CGR3,  0);  in _mx35_clocks_init()