Lines Matching full:gate
62 [ASPEED_CLK_GATE_MCLK] = { 0, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
63 [ASPEED_CLK_GATE_ECLK] = { 1, -1, "eclk-gate", "eclk", 0 }, /* Video Engine */
64 [ASPEED_CLK_GATE_GCLK] = { 2, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
66 [ASPEED_CLK_GATE_VCLK] = { 3, 6, "vclk-gate", NULL, 0 }, /* Video Capture */
67 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", 0 }, /* PCIe/PCI */
69 [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */
70 [ASPEED_CLK_GATE_REF0CLK] = { 6, -1, "ref0clk-gate", "clkin", CLK_IS_CRITICAL },
71 [ASPEED_CLK_GATE_USBPORT2CLK] = { 7, 3, "usb-port2-gate", NULL, 0 }, /* USB2.0 Host port 2 */
73 …[ASPEED_CLK_GATE_USBUHCICLK] = { 9, 15, "usb-uhci-gate", NULL, 0 }, /* USB1.1 (requires port 2 e…
75 [ASPEED_CLK_GATE_D1CLK] = { 10, 13, "d1clk-gate", "d1clk", 0 }, /* GFX CRT */
77 [ASPEED_CLK_GATE_YCLK] = { 13, 4, "yclk-gate", NULL, 0 }, /* HAC */
78 …[ASPEED_CLK_GATE_USBPORT1CLK] = { 14, 14, "usb-port1-gate", NULL, 0 }, /* USB2 hub/USB2 host port…
79 [ASPEED_CLK_GATE_UART5CLK] = { 15, -1, "uart5clk-gate", "uart", 0 }, /* UART5 */
81 [ASPEED_CLK_GATE_MAC1CLK] = { 20, 11, "mac1clk-gate", "mac12", 0 }, /* MAC1 */
82 [ASPEED_CLK_GATE_MAC2CLK] = { 21, 12, "mac2clk-gate", "mac12", 0 }, /* MAC2 */
84 [ASPEED_CLK_GATE_RSACLK] = { 24, 4, "rsaclk-gate", NULL, 0 }, /* HAC */
85 [ASPEED_CLK_GATE_RVASCLK] = { 25, 9, "rvasclk-gate", NULL, 0 }, /* RVAS */
87 [ASPEED_CLK_GATE_EMMCCLK] = { 27, 16, "emmcclk-gate", NULL, 0 }, /* For card clk */
89 [ASPEED_CLK_GATE_LCLK] = { 32, 32, "lclk-gate", NULL, 0 }, /* LPC */
90 [ASPEED_CLK_GATE_ESPICLK] = { 33, -1, "espiclk-gate", NULL, 0 }, /* eSPI */
91 [ASPEED_CLK_GATE_REF1CLK] = { 34, -1, "ref1clk-gate", "clkin", CLK_IS_CRITICAL },
93 [ASPEED_CLK_GATE_SDCLK] = { 36, 56, "sdclk-gate", NULL, 0 }, /* SDIO/SD */
94 [ASPEED_CLK_GATE_LHCCLK] = { 37, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */
97 [ASPEED_CLK_GATE_I3C0CLK] = { 40, 40, "i3c0clk-gate", NULL, 0 }, /* I3C0 */
98 [ASPEED_CLK_GATE_I3C1CLK] = { 41, 41, "i3c1clk-gate", NULL, 0 }, /* I3C1 */
99 [ASPEED_CLK_GATE_I3C2CLK] = { 42, 42, "i3c2clk-gate", NULL, 0 }, /* I3C2 */
100 [ASPEED_CLK_GATE_I3C3CLK] = { 43, 43, "i3c3clk-gate", NULL, 0 }, /* I3C3 */
101 [ASPEED_CLK_GATE_I3C4CLK] = { 44, 44, "i3c4clk-gate", NULL, 0 }, /* I3C4 */
102 [ASPEED_CLK_GATE_I3C5CLK] = { 45, 45, "i3c5clk-gate", NULL, 0 }, /* I3C5 */
103 [ASPEED_CLK_GATE_I3C6CLK] = { 46, 46, "i3c6clk-gate", NULL, 0 }, /* I3C6 */
104 [ASPEED_CLK_GATE_I3C7CLK] = { 47, 47, "i3c7clk-gate", NULL, 0 }, /* I3C7 */
105 [ASPEED_CLK_GATE_UART1CLK] = { 48, -1, "uart1clk-gate", "uart", 0 }, /* UART1 */
106 [ASPEED_CLK_GATE_UART2CLK] = { 49, -1, "uart2clk-gate", "uart", 0 }, /* UART2 */
107 [ASPEED_CLK_GATE_UART3CLK] = { 50, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */
108 [ASPEED_CLK_GATE_UART4CLK] = { 51, -1, "uart4clk-gate", "uart", 0 }, /* UART4 */
109 [ASPEED_CLK_GATE_MAC3CLK] = { 52, 52, "mac3clk-gate", "mac34", 0 }, /* MAC3 */
110 [ASPEED_CLK_GATE_MAC4CLK] = { 53, 53, "mac4clk-gate", "mac34", 0 }, /* MAC4 */
111 [ASPEED_CLK_GATE_UART6CLK] = { 54, -1, "uart6clk-gate", "uartx", 0 }, /* UART6 */
112 [ASPEED_CLK_GATE_UART7CLK] = { 55, -1, "uart7clk-gate", "uartx", 0 }, /* UART7 */
113 [ASPEED_CLK_GATE_UART8CLK] = { 56, -1, "uart8clk-gate", "uartx", 0 }, /* UART8 */
114 [ASPEED_CLK_GATE_UART9CLK] = { 57, -1, "uart9clk-gate", "uartx", 0 }, /* UART9 */
115 [ASPEED_CLK_GATE_UART10CLK] = { 58, -1, "uart10clk-gate", "uartx", 0 }, /* UART10 */
116 [ASPEED_CLK_GATE_UART11CLK] = { 59, -1, "uart11clk-gate", "uartx", 0 }, /* UART11 */
117 [ASPEED_CLK_GATE_UART12CLK] = { 60, -1, "uart12clk-gate", "uartx", 0 }, /* UART12 */
118 [ASPEED_CLK_GATE_UART13CLK] = { 61, -1, "uart13clk-gate", "uartx", 0 }, /* UART13 */
119 [ASPEED_CLK_GATE_FSICLK] = { 62, 59, "fsiclk-gate", NULL, 0 }, /* FSI */
215 static u32 get_reset_reg(struct aspeed_clk_gate *gate) in get_reset_reg() argument
217 if (gate->reset_idx < 32) in get_reset_reg()
223 static u32 get_clock_reg(struct aspeed_clk_gate *gate) in get_clock_reg() argument
225 if (gate->clock_idx < 32) in get_clock_reg()
233 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); in aspeed_g6_clk_is_enabled() local
234 u32 clk = get_bit(gate->clock_idx); in aspeed_g6_clk_is_enabled()
235 u32 rst = get_bit(gate->reset_idx); in aspeed_g6_clk_is_enabled()
245 if (gate->reset_idx >= 0) { in aspeed_g6_clk_is_enabled()
246 regmap_read(gate->map, get_reset_reg(gate), ®); in aspeed_g6_clk_is_enabled()
252 regmap_read(gate->map, get_clock_reg(gate), ®); in aspeed_g6_clk_is_enabled()
254 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk; in aspeed_g6_clk_is_enabled()
261 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); in aspeed_g6_clk_enable() local
263 u32 clk = get_bit(gate->clock_idx); in aspeed_g6_clk_enable()
264 u32 rst = get_bit(gate->reset_idx); in aspeed_g6_clk_enable()
266 spin_lock_irqsave(gate->lock, flags); in aspeed_g6_clk_enable()
269 spin_unlock_irqrestore(gate->lock, flags); in aspeed_g6_clk_enable()
273 if (gate->reset_idx >= 0) { in aspeed_g6_clk_enable()
275 regmap_write(gate->map, get_reset_reg(gate), rst); in aspeed_g6_clk_enable()
281 if (gate->flags & CLK_GATE_SET_TO_DISABLE) { in aspeed_g6_clk_enable()
283 regmap_write(gate->map, get_clock_reg(gate) + 0x04, clk); in aspeed_g6_clk_enable()
286 regmap_write(gate->map, get_clock_reg(gate), clk); in aspeed_g6_clk_enable()
289 if (gate->reset_idx >= 0) { in aspeed_g6_clk_enable()
293 regmap_write(gate->map, get_reset_reg(gate) + 0x4, rst); in aspeed_g6_clk_enable()
296 spin_unlock_irqrestore(gate->lock, flags); in aspeed_g6_clk_enable()
303 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); in aspeed_g6_clk_disable() local
305 u32 clk = get_bit(gate->clock_idx); in aspeed_g6_clk_disable()
307 spin_lock_irqsave(gate->lock, flags); in aspeed_g6_clk_disable()
309 if (gate->flags & CLK_GATE_SET_TO_DISABLE) { in aspeed_g6_clk_disable()
310 regmap_write(gate->map, get_clock_reg(gate), clk); in aspeed_g6_clk_disable()
313 regmap_write(gate->map, get_clock_reg(gate) + 0x4, clk); in aspeed_g6_clk_disable()
316 spin_unlock_irqrestore(gate->lock, flags); in aspeed_g6_clk_disable()
373 struct aspeed_clk_gate *gate; in aspeed_g6_clk_hw_register_gate() local
378 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in aspeed_g6_clk_hw_register_gate()
379 if (!gate) in aspeed_g6_clk_hw_register_gate()
388 gate->map = map; in aspeed_g6_clk_hw_register_gate()
389 gate->clock_idx = clock_idx; in aspeed_g6_clk_hw_register_gate()
390 gate->reset_idx = reset_idx; in aspeed_g6_clk_hw_register_gate()
391 gate->flags = clk_gate_flags; in aspeed_g6_clk_hw_register_gate()
392 gate->lock = lock; in aspeed_g6_clk_hw_register_gate()
393 gate->hw.init = &init; in aspeed_g6_clk_hw_register_gate()
395 hw = &gate->hw; in aspeed_g6_clk_hw_register_gate()
398 kfree(gate); in aspeed_g6_clk_hw_register_gate()
509 /* SD/SDIO clock divider and gate */ in aspeed_g6_clk_probe()