clk/bcm/clk-ns2.c

43 	.aon = AON_VAL(0x0, 1, 15, 12),
44 	.reset = RESET_VAL(0x4, 2, 1),
45 	.dig_filter = DF_VAL(0x0, 9, 3, 5, 4, 2, 3),
46 	.ndiv_int = REG_VAL(0x8, 4, 10),
47 	.pdiv = REG_VAL(0x8, 0, 4),
48 	.vco_ctrl = VCO_CTRL_VAL(0x10, 0xc),
49 	.status = REG_VAL(0x0, 27, 1),
56 	 * it to 0.
61 		.enable = ENABLE_VAL(0x0, 18, 12, 0),
62 		.mdiv = REG_VAL(0x18, 0, 8),
67 		.enable = ENABLE_VAL(0x0, 19, 13, 0),
68 		.mdiv = REG_VAL(0x18, 8, 8),
73 		.enable = ENABLE_VAL(0x0, 20, 14, 0),
74 		.mdiv = REG_VAL(0x14, 0, 8),
79 		.enable = ENABLE_VAL(0x0, 21, 15, 0),
80 		.mdiv = REG_VAL(0x14, 8, 8),
85 		.enable = ENABLE_VAL(0x0, 22, 16, 0),
86 		.mdiv = REG_VAL(0x14, 16, 8),
91 		.enable = ENABLE_VAL(0x0, 23, 17, 0),
92 		.mdiv = REG_VAL(0x14, 24, 8),
98 	iproc_pll_clk_setup(node, &genpll_scr, NULL, 0, genpll_scr_clk,  in ns2_genpll_scr_clk_init()
106 	.aon = AON_VAL(0x0, 1, 11, 10),
107 	.reset = RESET_VAL(0x4, 2, 1),
108 	.dig_filter = DF_VAL(0x0, 9, 3, 5, 4, 2, 3),
109 	.ndiv_int = REG_VAL(0x8, 4, 10),
110 	.pdiv = REG_VAL(0x8, 0, 4),
111 	.vco_ctrl = VCO_CTRL_VAL(0x10, 0xc),
112 	.status = REG_VAL(0x0, 13, 1),
118 	 * it to 0.
123 		.enable = ENABLE_VAL(0x0, 18, 12, 0),
124 		.mdiv = REG_VAL(0x18, 0, 8),
129 		.enable = ENABLE_VAL(0x0, 19, 13, 0),
130 		.mdiv = REG_VAL(0x18, 8, 8),
135 		.enable = ENABLE_VAL(0x0, 20, 14, 0),
136 		.mdiv = REG_VAL(0x14, 0, 8),
141 		.enable = ENABLE_VAL(0x0, 21, 15, 0),
142 		.mdiv = REG_VAL(0x14, 8, 8),
147 		.enable = ENABLE_VAL(0x0, 22, 16, 0),
148 		.mdiv = REG_VAL(0x14, 16, 8),
153 		.enable = ENABLE_VAL(0x0, 23, 17, 0),
154 		.mdiv = REG_VAL(0x14, 24, 8),
160 	iproc_pll_clk_setup(node, &genpll_sw, NULL, 0, genpll_sw_clk,  in ns2_genpll_sw_clk_init()
168 	.aon = AON_VAL(0x0, 2, 1, 0),
169 	.reset = RESET_VAL(0x4, 2, 1),
170 	.dig_filter = DF_VAL(0x0, 9, 3, 5, 4, 1, 4),
171 	.ndiv_int = REG_VAL(0x8, 4, 10),
172 	.pdiv = REG_VAL(0x8, 0, 4),
173 	.vco_ctrl = VCO_CTRL_VAL(0x10, 0xc),
174 	.status = REG_VAL(0x0, 0, 1),
180 	 * it to 0.
185 		.enable = ENABLE_VAL(0x0, 18, 12, 0),
186 		.mdiv = REG_VAL(0x14, 0, 8),
191 		.enable = ENABLE_VAL(0x0, 19, 13, 0),
192 		.mdiv = REG_VAL(0x14, 8, 8),
197 		.enable = ENABLE_VAL(0x0, 20, 14, 0),
198 		.mdiv = REG_VAL(0x10, 0, 8),
203 		.enable = ENABLE_VAL(0x0, 21, 15, 0),
204 		.mdiv = REG_VAL(0x10, 8, 8),
209 		.enable = ENABLE_VAL(0x0, 22, 16, 0),
210 		.mdiv = REG_VAL(0x10, 16, 8),
215 		.enable = ENABLE_VAL(0x0, 23, 17, 0),
216 		.mdiv = REG_VAL(0x10, 24, 8),
222 	iproc_pll_clk_setup(node, &lcpll_ddr, NULL, 0, lcpll_ddr_clk,  in ns2_lcpll_ddr_clk_init()
230 	.aon = AON_VAL(0x0, 2, 5, 4),
231 	.reset = RESET_VAL(0x4, 2, 1),
232 	.dig_filter = DF_VAL(0x0, 9, 3, 5, 4, 1, 4),
233 	.ndiv_int = REG_VAL(0x8, 4, 10),
234 	.pdiv = REG_VAL(0x8, 0, 4),
235 	.vco_ctrl = VCO_CTRL_VAL(0x10, 0xc),
236 	.status = REG_VAL(0x0, 0, 1),
242 	 * it to 0.
247 		.enable = ENABLE_VAL(0x0, 18, 12, 0),
248 		.mdiv = REG_VAL(0x14, 0, 8),
253 		.enable = ENABLE_VAL(0x0, 19, 13, 0),
254 		.mdiv = REG_VAL(0x14, 8, 8),
259 		.enable = ENABLE_VAL(0x0, 20, 14, 0),
260 		.mdiv = REG_VAL(0x10, 0, 8),
265 		.enable = ENABLE_VAL(0x0, 21, 15, 0),
266 		.mdiv = REG_VAL(0x10, 8, 8),
271 		.enable = ENABLE_VAL(0x0, 22, 16, 0),
272 		.mdiv = REG_VAL(0x10, 16, 8),
277 		.enable = ENABLE_VAL(0x0, 23, 17, 0),
278 		.mdiv = REG_VAL(0x10, 24, 8),
284 	iproc_pll_clk_setup(node, &lcpll_ports, NULL, 0, lcpll_ports_clk,  in ns2_lcpll_ports_clk_init()