clk/bcm/clk-kona.h

24 #include <linux/clk-provider.h>
28 /* The common clock framework uses u8 to represent a parent index */
32 #define BAD_CLK_NAME		((const char *)-1)
41 #define FLAG_SET(obj, type, flag)	((obj)->flags |= FLAG(type, flag))
42 #define FLAG_CLEAR(obj, type, flag)	((obj)->flags &= ~(FLAG(type, flag)))
43 #define FLAG_FLIP(obj, type, flag)	((obj)->flags ^= FLAG(type, flag))
44 #define FLAG_TEST(obj, type, flag)	(!!((obj)->flags & FLAG(type, flag)))
48 #define ccu_policy_exists(ccu_policy)	((ccu_policy)->enable.offset != 0)
52 #define policy_exists(policy)		((policy)->offset != 0)
63 #define hyst_exists(hyst)		((hyst)->offset != 0)
68 						(div)->u.s.frac_width > 0)
70 #define selector_exists(sel)		((sel)->width != 0)
73 #define policy_lvm_en_exists(enable)	((enable)->offset != 0)
74 #define policy_ctl_exists(control)	((control)->offset != 0)  argument
85  * CCU policy control for clocks.  Clocks can be enabled or disabled
106  * Gating control and status is managed by a 32-bit gate register.
109  * - (no gate)
111  * - hardware-only gating (auto-gating)
115  *     of auto-gated clocks can be read from the gate status bit.
116  * - software-only gating
117  *     Auto-gating is not available for this type of clock.
120  *     under software control can be read from the gate status bit.
124  * - selectable hardware or software gating
126  *     under software or hardware control.  Which type is in use is
139  *   HW         means this gate can be auto-gated
141  *   NO_DISABLE means this gate is (only) enabled if under software control
142  *   SW_MANAGED means the status of this gate is under software control
143  *   ENABLED    means this software-managed gate is *supposed* to be enabled
146 #define BCM_CLK_GATE_FLAGS_HW		((u32)1 << 1)	/* Can auto-gate */
147 #define BCM_CLK_GATE_FLAGS_SW		((u32)1 << 2)	/* Software control */
149 #define BCM_CLK_GATE_FLAGS_SW_MANAGED	((u32)1 << 4)	/* SW now in control */
155  * Any gate initially under software control will be enabled.
158 /* A hardware/software gate initially under software control */
170 /* A hardware/software gate initially under hardware control */
181 /* A hardware-or-enabled gate (enabled if not under hardware control) */
192 /* A software-only gate */
202 /* A hardware-only gate */
229  * variable.  If there are two dividers, they are the "pre-divider"
231  * there is no pre-divider.
233  * A fixed divider is any non-zero (positive) value, and it
236  * The value of a variable divider is maintained in a sub-field of a
237  * 32-bit divider register.  The position of the field in the
243  * bits comprise the low-order portion of the divider field, and can
246  * fractional bits.  Variable dividers with non-zero fraction width
248  * added 1 does *not* affect the low-order bit in this case, it
255  * been left-shifted by the fractional width of a divider.  Dividing
276 		u32 fixed;	/* non-zero fixed divider value */
284  *   FIXED means it is a fixed-rate divider
287 #define BCM_CLK_DIV_FLAGS_FIXED		((u32)1 << 1)	/* Fixed-value */
291 /* A fixed (non-zero) divider */
320  * Clocks may have multiple "parent" clocks.  If there is more than
321  * one, a selector must be specified to define which of the parent
323  * sub-field of a 32-bit selector register.  The range of
325  * available parent clocks.  Occasionally the reset value of a
329  * We register all known parent clocks with the common clock code
330  * using a packed array (i.e., no empty slots) of (parent) clock
345 	u32 *parent_sel;	/* array of parent selector values */
367  * case, the "pre-trigger" will be used when changing a clock's
368  * selector and/or its pre-divider.
402 #define NO_CLOCKS	{ NULL, }	/* Must use of no parent clocks */
431  * CCU policy control.  To enable software update of the policy
455 /* Policy control initialization macro */
466 	struct bcm_policy_ctl control;  member