Lines Matching +full:0 +full:x5a000000
39 #define CM_PASSWORD 0x5a000000
41 #define CM_GNRICCTL 0x000
42 #define CM_GNRICDIV 0x004
44 # define CM_DIV_FRAC_MASK GENMASK(CM_DIV_FRAC_BITS - 1, 0)
46 #define CM_VPUCTL 0x008
47 #define CM_VPUDIV 0x00c
48 #define CM_SYSCTL 0x010
49 #define CM_SYSDIV 0x014
50 #define CM_PERIACTL 0x018
51 #define CM_PERIADIV 0x01c
52 #define CM_PERIICTL 0x020
53 #define CM_PERIIDIV 0x024
54 #define CM_H264CTL 0x028
55 #define CM_H264DIV 0x02c
56 #define CM_ISPCTL 0x030
57 #define CM_ISPDIV 0x034
58 #define CM_V3DCTL 0x038
59 #define CM_V3DDIV 0x03c
60 #define CM_CAM0CTL 0x040
61 #define CM_CAM0DIV 0x044
62 #define CM_CAM1CTL 0x048
63 #define CM_CAM1DIV 0x04c
64 #define CM_CCP2CTL 0x050
65 #define CM_CCP2DIV 0x054
66 #define CM_DSI0ECTL 0x058
67 #define CM_DSI0EDIV 0x05c
68 #define CM_DSI0PCTL 0x060
69 #define CM_DSI0PDIV 0x064
70 #define CM_DPICTL 0x068
71 #define CM_DPIDIV 0x06c
72 #define CM_GP0CTL 0x070
73 #define CM_GP0DIV 0x074
74 #define CM_GP1CTL 0x078
75 #define CM_GP1DIV 0x07c
76 #define CM_GP2CTL 0x080
77 #define CM_GP2DIV 0x084
78 #define CM_HSMCTL 0x088
79 #define CM_HSMDIV 0x08c
80 #define CM_OTPCTL 0x090
81 #define CM_OTPDIV 0x094
82 #define CM_PCMCTL 0x098
83 #define CM_PCMDIV 0x09c
84 #define CM_PWMCTL 0x0a0
85 #define CM_PWMDIV 0x0a4
86 #define CM_SLIMCTL 0x0a8
87 #define CM_SLIMDIV 0x0ac
88 #define CM_SMICTL 0x0b0
89 #define CM_SMIDIV 0x0b4
90 /* no definition for 0x0b8 and 0x0bc */
91 #define CM_TCNTCTL 0x0c0
93 #define CM_TCNTCNT 0x0c4
94 #define CM_TECCTL 0x0c8
95 #define CM_TECDIV 0x0cc
96 #define CM_TD0CTL 0x0d0
97 #define CM_TD0DIV 0x0d4
98 #define CM_TD1CTL 0x0d8
99 #define CM_TD1DIV 0x0dc
100 #define CM_TSENSCTL 0x0e0
101 #define CM_TSENSDIV 0x0e4
102 #define CM_TIMERCTL 0x0e8
103 #define CM_TIMERDIV 0x0ec
104 #define CM_UARTCTL 0x0f0
105 #define CM_UARTDIV 0x0f4
106 #define CM_VECCTL 0x0f8
107 #define CM_VECDIV 0x0fc
108 #define CM_PULSECTL 0x190
109 #define CM_PULSEDIV 0x194
110 #define CM_SDCCTL 0x1a8
111 #define CM_SDCDIV 0x1ac
112 #define CM_ARMCTL 0x1b0
113 #define CM_AVEOCTL 0x1b8
114 #define CM_AVEODIV 0x1bc
115 #define CM_EMMCCTL 0x1c0
116 #define CM_EMMCDIV 0x1c4
117 #define CM_EMMC2CTL 0x1d0
118 #define CM_EMMC2DIV 0x1d4
128 # define CM_SRC_SHIFT 0
130 # define CM_SRC_MASK 0xf
131 # define CM_SRC_GND 0
146 #define CM_OSCCOUNT 0x100
148 #define CM_PLLA 0x104
157 # define CM_PLLA_LOADDSI0 BIT(0)
159 #define CM_PLLC 0x108
167 # define CM_PLLC_LOADCORE0 BIT(0)
169 #define CM_PLLD 0x10c
177 # define CM_PLLD_LOADDSI0 BIT(0)
179 #define CM_PLLH 0x110
182 # define CM_PLLH_LOADPIX BIT(0)
184 #define CM_LOCK 0x114
191 #define CM_EVENT 0x118
192 #define CM_DSI1ECTL 0x158
193 #define CM_DSI1EDIV 0x15c
194 #define CM_DSI1PCTL 0x160
195 #define CM_DSI1PDIV 0x164
196 #define CM_DFTCTL 0x168
197 #define CM_DFTDIV 0x16c
199 #define CM_PLLB 0x170
201 # define CM_PLLB_LOADARM BIT(0)
203 #define A2W_PLLA_CTRL 0x1100
204 #define A2W_PLLC_CTRL 0x1120
205 #define A2W_PLLD_CTRL 0x1140
206 #define A2W_PLLH_CTRL 0x1160
207 #define A2W_PLLB_CTRL 0x11e0
210 # define A2W_PLL_CTRL_PDIV_MASK 0x000007000
212 # define A2W_PLL_CTRL_NDIV_MASK 0x0000003ff
213 # define A2W_PLL_CTRL_NDIV_SHIFT 0
215 #define A2W_PLLA_ANA0 0x1010
216 #define A2W_PLLC_ANA0 0x1030
217 #define A2W_PLLD_ANA0 0x1050
218 #define A2W_PLLH_ANA0 0x1070
219 #define A2W_PLLB_ANA0 0x10f0
232 #define A2W_PLLH_KI_HIGH_SHIFT 0
233 #define A2W_PLLH_KI_HIGH_MASK GENMASK(0, 0)
237 #define A2W_XOSC_CTRL 0x1190
245 # define A2W_XOSC_CTRL_PLLC_ENABLE BIT(0)
247 #define A2W_PLLA_FRAC 0x1200
248 #define A2W_PLLC_FRAC 0x1220
249 #define A2W_PLLD_FRAC 0x1240
250 #define A2W_PLLH_FRAC 0x1260
251 #define A2W_PLLB_FRAC 0x12e0
257 #define A2W_PLL_DIV_SHIFT 0
259 #define A2W_PLLA_DSI0 0x1300
260 #define A2W_PLLA_CORE 0x1400
261 #define A2W_PLLA_PER 0x1500
262 #define A2W_PLLA_CCP2 0x1600
264 #define A2W_PLLC_CORE2 0x1320
265 #define A2W_PLLC_CORE1 0x1420
266 #define A2W_PLLC_PER 0x1520
267 #define A2W_PLLC_CORE0 0x1620
269 #define A2W_PLLD_DSI0 0x1340
270 #define A2W_PLLD_CORE 0x1440
271 #define A2W_PLLD_PER 0x1540
272 #define A2W_PLLD_DSI1 0x1640
274 #define A2W_PLLH_AUX 0x1360
275 #define A2W_PLLH_RCAL 0x1460
276 #define A2W_PLLH_PIX 0x1560
277 #define A2W_PLLH_STS 0x1660
279 #define A2W_PLLH_CTRLR 0x1960
280 #define A2W_PLLH_FRACR 0x1a60
281 #define A2W_PLLH_AUXR 0x1b60
282 #define A2W_PLLH_RCALR 0x1c60
283 #define A2W_PLLH_PIXR 0x1d60
284 #define A2W_PLLH_STSR 0x1e60
286 #define A2W_PLLB_ARM 0x13e0
287 #define A2W_PLLB_SP0 0x14e0
288 #define A2W_PLLB_SP1 0x15e0
289 #define A2W_PLLB_SP2 0x16e0
294 #define SOC_BCM2835 BIT(0)
372 count = 0; in bcm2835_measure_tcnt_mux()
383 count = 0; in bcm2835_measure_tcnt_mux()
391 cprman_write(cprman, CM_TCNTCTL, 0); in bcm2835_measure_tcnt_mux()
449 .mask0 = 0,
450 .set0 = 0,
463 .mask3 = 0,
464 .set3 = 0,
539 return 0; in bcm2835_pll_get_prediv_mask()
562 if (pdiv == 0) in bcm2835_pll_rate_from_divisors()
563 return 0; in bcm2835_pll_rate_from_divisors()
594 if (parent_rate == 0) in bcm2835_pll_get_rate()
595 return 0; in bcm2835_pll_get_rate()
658 return 0; in bcm2835_pll_on()
674 for (i = 3; i >= 0; i--) in bcm2835_pll_write_ana()
699 for (i = 3; i >= 0; i--) in bcm2835_pll_set_rate()
704 ana[0] &= ~data->ana->mask0; in bcm2835_pll_set_rate()
705 ana[0] |= data->ana->set0; in bcm2835_pll_set_rate()
744 return 0; in bcm2835_pll_set_rate()
759 regs[0].name = "cm_ctrl"; in bcm2835_pll_debug_init()
760 regs[0].offset = data->cm_ctrl_reg; in bcm2835_pll_debug_init()
766 regs[3].offset = data->ana_reg_base + 0 * 4; in bcm2835_pll_debug_init()
774 bcm2835_debugfs_regset(cprman, 0, regs, 7, dentry); in bcm2835_pll_debug_init()
852 return 0; in bcm2835_pll_divider_on()
868 div = 0; in bcm2835_pll_divider_set_rate()
875 return 0; in bcm2835_pll_divider_set_rate()
890 regs[0].name = "cm"; in bcm2835_pll_divider_debug_init()
891 regs[0].offset = data->cm_reg; in bcm2835_pll_divider_debug_init()
895 bcm2835_debugfs_regset(cprman, 0, regs, 2, dentry); in bcm2835_pll_divider_debug_init()
931 return (cprman_read(cprman, data->ctl_reg) & CM_ENABLE) != 0; in bcm2835_clock_is_on()
942 GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1; in bcm2835_clock_choose_div()
951 if (round_up && ((div & unused_frac_mask) != 0 || rem != 0)) in bcm2835_clock_choose_div()
983 if (data->int_bits == 0 && data->frac_bits == 0) in bcm2835_clock_rate_from_divisor()
993 if (div == 0) in bcm2835_clock_rate_from_divisor()
994 return 0; in bcm2835_clock_rate_from_divisor()
1011 if (data->int_bits == 0 && data->frac_bits == 0) in bcm2835_clock_get_rate()
1074 return 0; in bcm2835_clock_on()
1097 ctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0; in bcm2835_clock_set_rate()
1104 return 0; in bcm2835_clock_set_rate()
1113 return strncmp(clk_hw_get_name(hw), "pllc", 4) == 0; in bcm2835_clk_is_pllc()
1126 unsigned long best_rate = 0; in bcm2835_clock_choose_div_and_prate()
1191 unsigned long rate, best_rate = 0; in bcm2835_clock_determine_rate()
1192 unsigned long prate, best_prate = 0; in bcm2835_clock_determine_rate()
1193 unsigned long avgrate, best_avgrate = 0; in bcm2835_clock_determine_rate()
1202 for (i = 0; i < clk_hw_get_num_parents(hw); ++i) { in bcm2835_clock_determine_rate()
1236 return 0; in bcm2835_clock_determine_rate()
1247 return 0; in bcm2835_clock_set_parent()
1263 .offset = 0,
1323 memset(&init, 0, sizeof(init)); in bcm2835_register_pll()
1326 init.parent_names = &cprman->real_parent_names[0]; in bcm2835_register_pll()
1367 memset(&init, 0, sizeof(init)); in bcm2835_register_pll_divider()
1424 for (i = 0; i < clock_data->num_mux_parents; i++) { in bcm2835_register_clock()
1430 if (ret >= 0) in bcm2835_register_clock()
1434 memset(&init, 0, sizeof(init)); in bcm2835_register_clock()
1483 CM_GATE_BIT, 0, &cprman->regs_lock); in bcm2835_register_gate()
1889 .hold_mask = 0,
1899 .hold_mask = 0,
1909 .hold_mask = 0,
1924 .frac_bits = 0,
1947 .frac_bits = 0),
1954 .frac_bits = 0),
1984 .frac_bits = 0,
2018 .frac_bits = 0,
2042 .frac_bits = 0),
2162 .frac_bits = 0,
2192 .int_bits = 0,
2193 .frac_bits = 0,
2200 .int_bits = 0,
2201 .frac_bits = 0,
2261 cprman->regs = devm_platform_ioremap_resource(pdev, 0); in bcm2835_clk_probe()
2277 if (!cprman->real_parent_names[0]) in bcm2835_clk_probe()
2286 for (i = 0; i < asize; i++) { in bcm2835_clk_probe()