Lines Matching full:channel
113 "Malformed message (skipping): opcode=%d, channel=%03x, dir=%d, bufno=%03x, data=%07x\n", in malformed_message()
131 struct xilly_channel *channel; in xillybus_isr() local
191 channel = ep->channels[msg_channel]; in xillybus_isr()
193 if (msg_dir) { /* Write channel */ in xillybus_isr()
194 if (msg_bufno >= channel->num_wr_buffers) { in xillybus_isr()
198 spin_lock(&channel->wr_spinlock); in xillybus_isr()
199 channel->wr_buffers[msg_bufno]->end_offset = in xillybus_isr()
201 channel->wr_fpga_buf_idx = msg_bufno; in xillybus_isr()
202 channel->wr_empty = 0; in xillybus_isr()
203 channel->wr_sleepy = 0; in xillybus_isr()
204 spin_unlock(&channel->wr_spinlock); in xillybus_isr()
206 wake_up_interruptible(&channel->wr_wait); in xillybus_isr()
209 /* Read channel */ in xillybus_isr()
211 if (msg_bufno >= channel->num_rd_buffers) { in xillybus_isr()
216 spin_lock(&channel->rd_spinlock); in xillybus_isr()
217 channel->rd_fpga_buf_idx = msg_bufno; in xillybus_isr()
218 channel->rd_full = 0; in xillybus_isr()
219 spin_unlock(&channel->rd_spinlock); in xillybus_isr()
221 wake_up_interruptible(&channel->rd_wait); in xillybus_isr()
222 if (!channel->rd_synchronous) in xillybus_isr()
225 &channel->rd_workitem, in xillybus_isr()
238 channel = ep->channels[msg_channel]; in xillybus_isr()
240 if (msg_bufno >= channel->num_wr_buffers) { in xillybus_isr()
244 spin_lock(&channel->wr_spinlock); in xillybus_isr()
245 if (msg_bufno == channel->wr_host_buf_idx) in xillybus_isr()
246 channel->wr_ready = 1; in xillybus_isr()
247 spin_unlock(&channel->wr_spinlock); in xillybus_isr()
249 wake_up_interruptible(&channel->wr_ready_wait); in xillybus_isr()
264 channel = ep->channels[msg_channel]; in xillybus_isr()
265 spin_lock(&channel->wr_spinlock); in xillybus_isr()
266 channel->wr_eof = msg_bufno; in xillybus_isr()
267 channel->wr_sleepy = 0; in xillybus_isr()
269 channel->wr_hangup = channel->wr_empty && in xillybus_isr()
270 (channel->wr_host_buf_idx == msg_bufno); in xillybus_isr()
272 spin_unlock(&channel->wr_spinlock); in xillybus_isr()
274 wake_up_interruptible(&channel->wr_wait); in xillybus_isr()
408 struct xilly_channel *channel; in xilly_setupchannels() local
431 channel = devm_kcalloc(dev, ep->num_channels, in xilly_setupchannels()
433 if (!channel) in xilly_setupchannels()
442 ep->channels[0] = NULL; /* Channel 0 is message buf. */ in xilly_setupchannels()
447 channel->wr_buffers = NULL; in xilly_setupchannels()
448 channel->rd_buffers = NULL; in xilly_setupchannels()
449 channel->num_wr_buffers = 0; in xilly_setupchannels()
450 channel->num_rd_buffers = 0; in xilly_setupchannels()
451 channel->wr_fpga_buf_idx = -1; in xilly_setupchannels()
452 channel->wr_host_buf_idx = 0; in xilly_setupchannels()
453 channel->wr_host_buf_pos = 0; in xilly_setupchannels()
454 channel->wr_empty = 1; in xilly_setupchannels()
455 channel->wr_ready = 0; in xilly_setupchannels()
456 channel->wr_sleepy = 1; in xilly_setupchannels()
457 channel->rd_fpga_buf_idx = 0; in xilly_setupchannels()
458 channel->rd_host_buf_idx = 0; in xilly_setupchannels()
459 channel->rd_host_buf_pos = 0; in xilly_setupchannels()
460 channel->rd_full = 0; in xilly_setupchannels()
461 channel->wr_ref_count = 0; in xilly_setupchannels()
462 channel->rd_ref_count = 0; in xilly_setupchannels()
464 spin_lock_init(&channel->wr_spinlock); in xilly_setupchannels()
465 spin_lock_init(&channel->rd_spinlock); in xilly_setupchannels()
466 mutex_init(&channel->wr_mutex); in xilly_setupchannels()
467 mutex_init(&channel->rd_mutex); in xilly_setupchannels()
468 init_waitqueue_head(&channel->rd_wait); in xilly_setupchannels()
469 init_waitqueue_head(&channel->wr_wait); in xilly_setupchannels()
470 init_waitqueue_head(&channel->wr_ready_wait); in xilly_setupchannels()
472 INIT_DELAYED_WORK(&channel->rd_workitem, xillybus_autoflush); in xilly_setupchannels()
474 channel->endpoint = ep; in xilly_setupchannels()
475 channel->chan_num = i; in xilly_setupchannels()
477 channel->log2_element_size = 0; in xilly_setupchannels()
479 ep->channels[i] = channel++; in xilly_setupchannels()
499 "IDT requests channel out of range. Aborting.\n"); in xilly_setupchannels()
503 channel = ep->channels[channelnum]; /* NULL for msg channel */ in xilly_setupchannels()
506 channel->log2_element_size = ((format > 2) ? in xilly_setupchannels()
510 (1 << channel->log2_element_size); in xilly_setupchannels()
522 channel->num_rd_buffers = bufnum; in xilly_setupchannels()
523 channel->rd_buf_size = bytebufsize; in xilly_setupchannels()
524 channel->rd_allow_partial = allowpartial; in xilly_setupchannels()
525 channel->rd_synchronous = synchronous; in xilly_setupchannels()
526 channel->rd_exclusive_open = exclusive_open; in xilly_setupchannels()
527 channel->seekable = seekable; in xilly_setupchannels()
529 channel->rd_buffers = buffers; in xilly_setupchannels()
533 channel->num_wr_buffers = bufnum; in xilly_setupchannels()
534 channel->wr_buf_size = bytebufsize; in xilly_setupchannels()
536 channel->seekable = seekable; in xilly_setupchannels()
537 channel->wr_supports_nonempty = supports_nonempty; in xilly_setupchannels()
539 channel->wr_allow_partial = allowpartial; in xilly_setupchannels()
540 channel->wr_synchronous = synchronous; in xilly_setupchannels()
541 channel->wr_exclusive_open = exclusive_open; in xilly_setupchannels()
543 channel->wr_buffers = buffers; in xilly_setupchannels()
609 struct xilly_channel *channel; in xilly_obtain_idt() local
613 channel = endpoint->channels[1]; /* This should be generated ad-hoc */ in xilly_obtain_idt()
615 channel->wr_sleepy = 1; in xilly_obtain_idt()
618 (3 << 24), /* Opcode 3 for channel 0 = Send IDT */ in xilly_obtain_idt()
621 t = wait_event_interruptible_timeout(channel->wr_wait, in xilly_obtain_idt()
622 (!channel->wr_sleepy), in xilly_obtain_idt()
635 channel->endpoint, in xilly_obtain_idt()
636 channel->wr_buffers[0]->dma_addr, in xilly_obtain_idt()
637 channel->wr_buf_size, in xilly_obtain_idt()
640 if (channel->wr_buffers[0]->end_offset != endpoint->idtlen) { in xilly_obtain_idt()
643 channel->wr_buffers[0]->end_offset, endpoint->idtlen); in xilly_obtain_idt()
647 if (crc32_le(~0, channel->wr_buffers[0]->addr, in xilly_obtain_idt()
653 version = channel->wr_buffers[0]->addr; in xilly_obtain_idt()
674 struct xilly_channel *channel = filp->private_data; in xillybus_read() local
682 if (channel->endpoint->fatal_error) in xillybus_read()
687 rc = mutex_lock_interruptible(&channel->wr_mutex); in xillybus_read()
694 spin_lock_irqsave(&channel->wr_spinlock, flags); in xillybus_read()
696 empty = channel->wr_empty; in xillybus_read()
697 ready = !empty || channel->wr_ready; in xillybus_read()
700 bufidx = channel->wr_host_buf_idx; in xillybus_read()
701 bufpos = channel->wr_host_buf_pos; in xillybus_read()
702 howmany = ((channel->wr_buffers[bufidx]->end_offset in xillybus_read()
703 + 1) << channel->log2_element_size) in xillybus_read()
711 channel->wr_host_buf_pos += howmany; in xillybus_read()
715 channel->wr_host_buf_pos = 0; in xillybus_read()
717 if (bufidx == channel->wr_fpga_buf_idx) { in xillybus_read()
718 channel->wr_empty = 1; in xillybus_read()
719 channel->wr_sleepy = 1; in xillybus_read()
720 channel->wr_ready = 0; in xillybus_read()
723 if (bufidx >= (channel->num_wr_buffers - 1)) in xillybus_read()
724 channel->wr_host_buf_idx = 0; in xillybus_read()
726 channel->wr_host_buf_idx++; in xillybus_read()
738 reached_eof = channel->wr_empty && in xillybus_read()
739 (channel->wr_host_buf_idx == channel->wr_eof); in xillybus_read()
740 channel->wr_hangup = reached_eof; in xillybus_read()
741 exhausted = channel->wr_empty; in xillybus_read()
742 waiting_bufidx = channel->wr_host_buf_idx; in xillybus_read()
744 spin_unlock_irqrestore(&channel->wr_spinlock, flags); in xillybus_read()
749 channel->endpoint->ephw->hw_sync_sgl_for_cpu( in xillybus_read()
750 channel->endpoint, in xillybus_read()
751 channel->wr_buffers[bufidx]->dma_addr, in xillybus_read()
752 channel->wr_buf_size, in xillybus_read()
757 channel->wr_buffers[bufidx]->addr in xillybus_read()
765 channel->endpoint->ephw->hw_sync_sgl_for_device( in xillybus_read()
766 channel->endpoint, in xillybus_read()
767 channel->wr_buffers[bufidx]->dma_addr, in xillybus_read()
768 channel->wr_buf_size, in xillybus_read()
775 * and the certain channel is protected with in xillybus_read()
776 * the channel-specific mutex. in xillybus_read()
779 iowrite32(1 | (channel->chan_num << 1) | in xillybus_read()
781 channel->endpoint->registers + in xillybus_read()
786 mutex_unlock(&channel->wr_mutex); in xillybus_read()
800 (channel->wr_synchronous && channel->wr_allow_partial))) in xillybus_read()
830 channel->log2_element_size; in xillybus_read()
831 int buf_elements = channel->wr_buf_size >> in xillybus_read()
832 channel->log2_element_size; in xillybus_read()
839 if (channel->wr_synchronous) { in xillybus_read()
841 if (channel->wr_allow_partial && in xillybus_read()
846 if (!channel->wr_allow_partial && in xillybus_read()
848 (buf_elements * channel->num_wr_buffers))) in xillybus_read()
850 channel->num_wr_buffers - 1; in xillybus_read()
861 if (channel->wr_synchronous || in xillybus_read()
863 mutex_lock(&channel->endpoint->register_mutex); in xillybus_read()
866 channel->endpoint->registers + in xillybus_read()
869 iowrite32(1 | (channel->chan_num << 1) | in xillybus_read()
872 channel->endpoint->registers + in xillybus_read()
875 mutex_unlock(&channel->endpoint-> in xillybus_read()
886 if (!channel->wr_allow_partial || in xillybus_read()
895 mutex_unlock(&channel->wr_mutex); in xillybus_read()
898 channel->wr_wait, in xillybus_read()
899 (!channel->wr_sleepy))) in xillybus_read()
903 &channel->wr_mutex)) in xillybus_read()
905 } while (channel->wr_sleepy); in xillybus_read()
910 if (channel->endpoint->fatal_error) in xillybus_read()
930 channel->wr_wait, in xillybus_read()
931 (!channel->wr_sleepy), in xillybus_read()
938 mutex_unlock(&channel->wr_mutex); in xillybus_read()
939 if (channel->endpoint->fatal_error) in xillybus_read()
958 iowrite32(1 | (channel->chan_num << 1) | in xillybus_read()
961 channel->endpoint->registers + in xillybus_read()
974 mutex_unlock(&channel->wr_mutex); in xillybus_read()
976 if (channel->endpoint->fatal_error) in xillybus_read()
992 static int xillybus_myflush(struct xilly_channel *channel, long timeout) in xillybus_myflush() argument
1003 if (channel->endpoint->fatal_error) in xillybus_myflush()
1005 rc = mutex_lock_interruptible(&channel->rd_mutex); in xillybus_myflush()
1010 * Don't flush a closed channel. This can happen when the work queued in xillybus_myflush()
1015 if (!channel->rd_ref_count) in xillybus_myflush()
1018 bufidx = channel->rd_host_buf_idx; in xillybus_myflush()
1021 channel->num_rd_buffers - 1 : in xillybus_myflush()
1024 end_offset_plus1 = channel->rd_host_buf_pos >> in xillybus_myflush()
1025 channel->log2_element_size; in xillybus_myflush()
1027 new_rd_host_buf_pos = channel->rd_host_buf_pos - in xillybus_myflush()
1028 (end_offset_plus1 << channel->log2_element_size); in xillybus_myflush()
1032 unsigned char *tail = channel->rd_buffers[bufidx]->addr + in xillybus_myflush()
1033 (end_offset_plus1 << channel->log2_element_size); in xillybus_myflush()
1037 channel->rd_leftovers[i] = *tail++; in xillybus_myflush()
1039 spin_lock_irqsave(&channel->rd_spinlock, flags); in xillybus_myflush()
1044 (channel->rd_full || in xillybus_myflush()
1045 (bufidx_minus1 != channel->rd_fpga_buf_idx))) { in xillybus_myflush()
1046 spin_unlock_irqrestore(&channel->rd_spinlock, flags); in xillybus_myflush()
1056 channel->rd_leftovers[3] = (new_rd_host_buf_pos != 0); in xillybus_myflush()
1060 if (bufidx == channel->rd_fpga_buf_idx) in xillybus_myflush()
1061 channel->rd_full = 1; in xillybus_myflush()
1062 spin_unlock_irqrestore(&channel->rd_spinlock, flags); in xillybus_myflush()
1064 if (bufidx >= (channel->num_rd_buffers - 1)) in xillybus_myflush()
1065 channel->rd_host_buf_idx = 0; in xillybus_myflush()
1067 channel->rd_host_buf_idx++; in xillybus_myflush()
1069 channel->endpoint->ephw->hw_sync_sgl_for_device( in xillybus_myflush()
1070 channel->endpoint, in xillybus_myflush()
1071 channel->rd_buffers[bufidx]->dma_addr, in xillybus_myflush()
1072 channel->rd_buf_size, in xillybus_myflush()
1075 mutex_lock(&channel->endpoint->register_mutex); in xillybus_myflush()
1078 channel->endpoint->registers + fpga_buf_offset_reg); in xillybus_myflush()
1080 iowrite32((channel->chan_num << 1) | /* Channel ID */ in xillybus_myflush()
1083 channel->endpoint->registers + fpga_buf_ctrl_reg); in xillybus_myflush()
1085 mutex_unlock(&channel->endpoint->register_mutex); in xillybus_myflush()
1087 bufidx = channel->num_rd_buffers - 1; in xillybus_myflush()
1092 channel->rd_host_buf_pos = new_rd_host_buf_pos; in xillybus_myflush()
1100 * channel->rd_host_buf_idx the one after it. in xillybus_myflush()
1102 * If bufidx == channel->rd_fpga_buf_idx we're either empty or full. in xillybus_myflush()
1106 spin_lock_irqsave(&channel->rd_spinlock, flags); in xillybus_myflush()
1108 if (bufidx != channel->rd_fpga_buf_idx) in xillybus_myflush()
1109 channel->rd_full = 1; /* in xillybus_myflush()
1114 empty = !channel->rd_full; in xillybus_myflush()
1116 spin_unlock_irqrestore(&channel->rd_spinlock, flags); in xillybus_myflush()
1127 wait_event_interruptible(channel->rd_wait, in xillybus_myflush()
1128 (!channel->rd_full)); in xillybus_myflush()
1131 channel->rd_wait, in xillybus_myflush()
1132 (!channel->rd_full), in xillybus_myflush()
1134 dev_warn(channel->endpoint->dev, in xillybus_myflush()
1141 if (channel->rd_full) { in xillybus_myflush()
1148 mutex_unlock(&channel->rd_mutex); in xillybus_myflush()
1150 if (channel->endpoint->fatal_error) in xillybus_myflush()
1168 struct xilly_channel *channel = container_of( in xillybus_autoflush() local
1172 rc = xillybus_myflush(channel, -1); in xillybus_autoflush()
1174 dev_warn(channel->endpoint->dev, in xillybus_autoflush()
1177 dev_err(channel->endpoint->dev, in xillybus_autoflush()
1187 struct xilly_channel *channel = filp->private_data; in xillybus_write() local
1195 if (channel->endpoint->fatal_error) in xillybus_write()
1198 rc = mutex_lock_interruptible(&channel->rd_mutex); in xillybus_write()
1205 spin_lock_irqsave(&channel->rd_spinlock, flags); in xillybus_write()
1207 full = channel->rd_full; in xillybus_write()
1210 bufidx = channel->rd_host_buf_idx; in xillybus_write()
1211 bufpos = channel->rd_host_buf_pos; in xillybus_write()
1212 howmany = channel->rd_buf_size - bufpos; in xillybus_write()
1222 ((bufpos >> channel->log2_element_size) == 0))) { in xillybus_write()
1226 channel->rd_host_buf_pos += howmany; in xillybus_write()
1232 channel->rd_buf_size >> in xillybus_write()
1233 channel->log2_element_size; in xillybus_write()
1234 channel->rd_host_buf_pos = 0; in xillybus_write()
1242 channel->log2_element_size; in xillybus_write()
1244 channel->rd_host_buf_pos -= in xillybus_write()
1246 channel->log2_element_size; in xillybus_write()
1248 tail = channel-> in xillybus_write()
1251 channel->log2_element_size); in xillybus_write()
1254 i < channel->rd_host_buf_pos; in xillybus_write()
1256 channel->rd_leftovers[i] = in xillybus_write()
1260 if (bufidx == channel->rd_fpga_buf_idx) in xillybus_write()
1261 channel->rd_full = 1; in xillybus_write()
1263 if (bufidx >= (channel->num_rd_buffers - 1)) in xillybus_write()
1264 channel->rd_host_buf_idx = 0; in xillybus_write()
1266 channel->rd_host_buf_idx++; in xillybus_write()
1278 exhausted = channel->rd_full; in xillybus_write()
1280 spin_unlock_irqrestore(&channel->rd_spinlock, flags); in xillybus_write()
1284 channel->rd_buffers[bufidx]->addr; in xillybus_write()
1288 (channel->rd_leftovers[3] != 0)) { in xillybus_write()
1289 channel->endpoint->ephw->hw_sync_sgl_for_cpu( in xillybus_write()
1290 channel->endpoint, in xillybus_write()
1291 channel->rd_buffers[bufidx]->dma_addr, in xillybus_write()
1292 channel->rd_buf_size, in xillybus_write()
1297 *head++ = channel->rd_leftovers[i]; in xillybus_write()
1299 channel->rd_leftovers[3] = 0; /* Clear flag */ in xillybus_write()
1303 channel->rd_buffers[bufidx]->addr + bufpos, in xillybus_write()
1311 channel->endpoint->ephw->hw_sync_sgl_for_device( in xillybus_write()
1312 channel->endpoint, in xillybus_write()
1313 channel->rd_buffers[bufidx]->dma_addr, in xillybus_write()
1314 channel->rd_buf_size, in xillybus_write()
1317 mutex_lock(&channel->endpoint->register_mutex); in xillybus_write()
1320 channel->endpoint->registers + in xillybus_write()
1323 iowrite32((channel->chan_num << 1) | in xillybus_write()
1326 channel->endpoint->registers + in xillybus_write()
1329 mutex_unlock(&channel->endpoint-> in xillybus_write()
1332 channel->rd_leftovers[3] = in xillybus_write()
1333 (channel->rd_host_buf_pos != 0); in xillybus_write()
1337 mutex_unlock(&channel->rd_mutex); in xillybus_write()
1339 if (channel->endpoint->fatal_error) in xillybus_write()
1342 if (!channel->rd_synchronous) in xillybus_write()
1345 &channel->rd_workitem, in xillybus_write()
1358 if ((bytes_done > 0) && channel->rd_allow_partial) in xillybus_write()
1372 if (wait_event_interruptible(channel->rd_wait, in xillybus_write()
1373 (!channel->rd_full))) { in xillybus_write()
1374 mutex_unlock(&channel->rd_mutex); in xillybus_write()
1376 if (channel->endpoint->fatal_error) in xillybus_write()
1385 mutex_unlock(&channel->rd_mutex); in xillybus_write()
1387 if (!channel->rd_synchronous) in xillybus_write()
1389 &channel->rd_workitem, in xillybus_write()
1392 if (channel->endpoint->fatal_error) in xillybus_write()
1398 if ((channel->rd_synchronous) && (bytes_done > 0)) { in xillybus_write()
1415 struct xilly_channel *channel; in xillybus_open() local
1439 channel = endpoint->channels[1 + minor - endpoint->lowest_minor]; in xillybus_open()
1440 filp->private_data = channel; in xillybus_open()
1448 if ((filp->f_mode & FMODE_READ) && (!channel->num_wr_buffers)) in xillybus_open()
1451 if ((filp->f_mode & FMODE_WRITE) && (!channel->num_rd_buffers)) in xillybus_open()
1455 (channel->wr_synchronous || !channel->wr_allow_partial || in xillybus_open()
1456 !channel->wr_supports_nonempty)) { in xillybus_open()
1463 (channel->rd_synchronous || !channel->rd_allow_partial)) { in xillybus_open()
1477 rc = mutex_lock_interruptible(&channel->wr_mutex); in xillybus_open()
1483 rc = mutex_lock_interruptible(&channel->rd_mutex); in xillybus_open()
1489 (channel->wr_ref_count != 0) && in xillybus_open()
1490 (channel->wr_exclusive_open)) { in xillybus_open()
1496 (channel->rd_ref_count != 0) && in xillybus_open()
1497 (channel->rd_exclusive_open)) { in xillybus_open()
1503 if (channel->wr_ref_count == 0) { /* First open of file */ in xillybus_open()
1505 spin_lock_irqsave(&channel->wr_spinlock, flags); in xillybus_open()
1506 channel->wr_host_buf_idx = 0; in xillybus_open()
1507 channel->wr_host_buf_pos = 0; in xillybus_open()
1508 channel->wr_fpga_buf_idx = -1; in xillybus_open()
1509 channel->wr_empty = 1; in xillybus_open()
1510 channel->wr_ready = 0; in xillybus_open()
1511 channel->wr_sleepy = 1; in xillybus_open()
1512 channel->wr_eof = -1; in xillybus_open()
1513 channel->wr_hangup = 0; in xillybus_open()
1515 spin_unlock_irqrestore(&channel->wr_spinlock, flags); in xillybus_open()
1517 iowrite32(1 | (channel->chan_num << 1) | in xillybus_open()
1518 (4 << 24) | /* Opcode 4, open channel */ in xillybus_open()
1519 ((channel->wr_synchronous & 1) << 23), in xillybus_open()
1520 channel->endpoint->registers + in xillybus_open()
1524 channel->wr_ref_count++; in xillybus_open()
1528 if (channel->rd_ref_count == 0) { /* First open of file */ in xillybus_open()
1530 spin_lock_irqsave(&channel->rd_spinlock, flags); in xillybus_open()
1531 channel->rd_host_buf_idx = 0; in xillybus_open()
1532 channel->rd_host_buf_pos = 0; in xillybus_open()
1533 channel->rd_leftovers[3] = 0; /* No leftovers. */ in xillybus_open()
1534 channel->rd_fpga_buf_idx = channel->num_rd_buffers - 1; in xillybus_open()
1535 channel->rd_full = 0; in xillybus_open()
1537 spin_unlock_irqrestore(&channel->rd_spinlock, flags); in xillybus_open()
1539 iowrite32((channel->chan_num << 1) | in xillybus_open()
1540 (4 << 24), /* Opcode 4, open channel */ in xillybus_open()
1541 channel->endpoint->registers + in xillybus_open()
1545 channel->rd_ref_count++; in xillybus_open()
1550 mutex_unlock(&channel->rd_mutex); in xillybus_open()
1553 mutex_unlock(&channel->wr_mutex); in xillybus_open()
1555 if (!rc && (!channel->seekable)) in xillybus_open()
1564 struct xilly_channel *channel = filp->private_data; in xillybus_release() local
1569 if (channel->endpoint->fatal_error) in xillybus_release()
1573 mutex_lock(&channel->rd_mutex); in xillybus_release()
1575 channel->rd_ref_count--; in xillybus_release()
1577 if (channel->rd_ref_count == 0) { in xillybus_release()
1583 iowrite32((channel->chan_num << 1) | /* Channel ID */ in xillybus_release()
1584 (5 << 24), /* Opcode 5, close channel */ in xillybus_release()
1585 channel->endpoint->registers + in xillybus_release()
1588 mutex_unlock(&channel->rd_mutex); in xillybus_release()
1592 mutex_lock(&channel->wr_mutex); in xillybus_release()
1594 channel->wr_ref_count--; in xillybus_release()
1596 if (channel->wr_ref_count == 0) { in xillybus_release()
1597 iowrite32(1 | (channel->chan_num << 1) | in xillybus_release()
1598 (5 << 24), /* Opcode 5, close channel */ in xillybus_release()
1599 channel->endpoint->registers + in xillybus_release()
1605 * the channel or because of a user's EOF), but verify in xillybus_release()
1613 spin_lock_irqsave(&channel->wr_spinlock, in xillybus_release()
1615 buf_idx = channel->wr_fpga_buf_idx; in xillybus_release()
1616 eof = channel->wr_eof; in xillybus_release()
1617 channel->wr_sleepy = 1; in xillybus_release()
1618 spin_unlock_irqrestore(&channel->wr_spinlock, in xillybus_release()
1628 if (buf_idx == channel->num_wr_buffers) in xillybus_release()
1643 channel->wr_wait, in xillybus_release()
1644 (!channel->wr_sleepy))) in xillybus_release()
1647 if (channel->wr_sleepy) { in xillybus_release()
1648 mutex_unlock(&channel->wr_mutex); in xillybus_release()
1649 dev_warn(channel->endpoint->dev, in xillybus_release()
1656 mutex_unlock(&channel->wr_mutex); in xillybus_release()
1664 struct xilly_channel *channel = filp->private_data; in xillybus_llseek() local
1675 if (channel->endpoint->fatal_error) in xillybus_llseek()
1678 mutex_lock(&channel->wr_mutex); in xillybus_llseek()
1679 mutex_lock(&channel->rd_mutex); in xillybus_llseek()
1697 if (pos & ((1 << channel->log2_element_size) - 1)) { in xillybus_llseek()
1702 mutex_lock(&channel->endpoint->register_mutex); in xillybus_llseek()
1704 iowrite32(pos >> channel->log2_element_size, in xillybus_llseek()
1705 channel->endpoint->registers + fpga_buf_offset_reg); in xillybus_llseek()
1707 iowrite32((channel->chan_num << 1) | in xillybus_llseek()
1709 channel->endpoint->registers + fpga_buf_ctrl_reg); in xillybus_llseek()
1711 mutex_unlock(&channel->endpoint->register_mutex); in xillybus_llseek()
1714 mutex_unlock(&channel->rd_mutex); in xillybus_llseek()
1715 mutex_unlock(&channel->wr_mutex); in xillybus_llseek()
1723 * Since seekable devices are allowed only when the channel is in xillybus_llseek()
1731 channel->rd_leftovers[3] = 0; in xillybus_llseek()
1738 struct xilly_channel *channel = filp->private_data; in xillybus_poll() local
1742 poll_wait(filp, &channel->endpoint->ep_wait, wait); in xillybus_poll()
1752 if (!channel->wr_synchronous && channel->wr_supports_nonempty) { in xillybus_poll()
1753 poll_wait(filp, &channel->wr_wait, wait); in xillybus_poll()
1754 poll_wait(filp, &channel->wr_ready_wait, wait); in xillybus_poll()
1756 spin_lock_irqsave(&channel->wr_spinlock, flags); in xillybus_poll()
1757 if (!channel->wr_empty || channel->wr_ready) in xillybus_poll()
1760 if (channel->wr_hangup) in xillybus_poll()
1767 spin_unlock_irqrestore(&channel->wr_spinlock, flags); in xillybus_poll()
1771 * If partial data write is disallowed on a write() channel, in xillybus_poll()
1776 if (channel->rd_allow_partial) { in xillybus_poll()
1777 poll_wait(filp, &channel->rd_wait, wait); in xillybus_poll()
1779 spin_lock_irqsave(&channel->rd_spinlock, flags); in xillybus_poll()
1780 if (!channel->rd_full) in xillybus_poll()
1782 spin_unlock_irqrestore(&channel->rd_spinlock, flags); in xillybus_poll()
1785 if (channel->endpoint->fatal_error) in xillybus_poll()