Lines Matching +full:exported +full:- +full:sram
14 * - One to configure the access of the CPU to the devices. Depending
20 * - One to configure the access to the CPU to the SDRAM. There are
26 * - Reads out the SDRAM address decoding windows at initialization
28 * informations. The exported function mv_mbus_dram_info() allow
33 * devices have to configure those device -> SDRAM windows to ensure
36 * - Provides an API for platform code or device drivers to
37 * dynamically add or remove address decoding windows for the CPU ->
42 * - Provides a debugfs interface in /sys/kernel/debug/mvebu-mbus/ to
43 * see the list of CPU -> SDRAM windows and their configuration
44 * (file 'sdram') and the list of CPU -> devices windows and their
159 * - The normal one, where the described DRAM ranges may overlap with
165 * - The 'nooverlap' one, where the described DRAM ranges are
170 * the crypto SRAM (which is mapped through an I/O window) and a
193 return mbus->soc->win_remap_offset(win) != MVEBU_MBUS_NO_REMAP; in mvebu_mbus_window_is_remappable()
205 void __iomem *addr = mbus->mbuswins_base + in mvebu_mbus_read_window()
206 mbus->soc->win_cfg_offset(win); in mvebu_mbus_read_window()
229 void __iomem *addr_rmp = mbus->mbuswins_base + in mvebu_mbus_read_window()
230 mbus->soc->win_remap_offset(win); in mvebu_mbus_read_window()
244 addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win); in mvebu_mbus_disable_window()
249 addr = mbus->mbuswins_base + mbus->soc->win_remap_offset(win); in mvebu_mbus_disable_window()
260 void __iomem *addr = mbus->mbuswins_base + in mvebu_mbus_window_is_free()
261 mbus->soc->win_cfg_offset(win); in mvebu_mbus_window_is_free()
278 for (win = 0; win < mbus->soc->num_wins; win++) { in mvebu_mbus_window_conflicts()
309 for (win = 0; win < mbus->soc->num_wins; win++) { in mvebu_mbus_find_window()
325 return -ENODEV; in mvebu_mbus_find_window()
333 void __iomem *addr = mbus->mbuswins_base + in mvebu_mbus_setup_window()
334 mbus->soc->win_cfg_offset(win); in mvebu_mbus_setup_window()
339 return -EINVAL; in mvebu_mbus_setup_window()
342 if ((base & (phys_addr_t)(size - 1)) != 0) { in mvebu_mbus_setup_window()
345 return -EINVAL; in mvebu_mbus_setup_window()
348 ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) | in mvebu_mbus_setup_window()
352 if (mbus->hw_io_coherency) in mvebu_mbus_setup_window()
359 void __iomem *addr_rmp = mbus->mbuswins_base + in mvebu_mbus_setup_window()
360 mbus->soc->win_remap_offset(win); in mvebu_mbus_setup_window()
381 for (win = 0; win < mbus->soc->num_wins; win++) { in mvebu_mbus_alloc_window()
392 for (win = 0; win < mbus->soc->num_wins; win++) { in mvebu_mbus_alloc_window()
403 return -ENOMEM; in mvebu_mbus_alloc_window()
417 u32 basereg = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i)); in mvebu_sdram_debug_show_orion()
418 u32 sizereg = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i)); in mvebu_sdram_debug_show_orion()
431 seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n", in mvebu_sdram_debug_show_orion()
447 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i)); in mvebu_sdram_debug_show_dove()
457 size = 0x100000 << (((map & 0x000f0000) >> 16) - 4); in mvebu_sdram_debug_show_dove()
459 seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n", in mvebu_sdram_debug_show_dove()
470 return mbus->soc->show_cpu_target(mbus, seq, v); in mvebu_sdram_debug_show()
475 return single_open(file, mvebu_sdram_debug_show, inode->i_private); in mvebu_sdram_debug_open()
490 for (win = 0; win < mbus->soc->num_wins; win++) { in mvebu_devs_debug_show()
505 seq_printf(seq, "[%02d] %016llx - %016llx : %04x:%04x", in mvebu_devs_debug_show()
510 ((wbase & (u64)(wsize - 1)) != 0)) in mvebu_devs_debug_show()
525 return single_open(file, mvebu_devs_debug_show, inode->i_private); in mvebu_devs_debug_open()
536 * SoC-specific functions and definitions
548 * - At offset 0x0, there are the registers for the first 8 in armada_370_xp_mbus_win_cfg_offset()
551 * - Then at offset 0x80, there is a hole of 0x10 bytes for in armada_370_xp_mbus_win_cfg_offset()
554 * - Then at offset 0x90, there the registers for 12 in armada_370_xp_mbus_win_cfg_offset()
561 return 0x90 + ((win - 8) << 3); in armada_370_xp_mbus_win_cfg_offset()
569 return 0x900 + ((win - 8) << 4); in mv78xx0_mbus_win_cfg_offset()
601 return 0xF0 - WIN_REMAP_LO_OFF; in armada_xp_mbus_win_remap_offset()
655 base = w->base; in mvebu_mbus_setup_cpu_target_nooverlap()
656 size = w->size; in mvebu_mbus_setup_cpu_target_nooverlap()
671 size -= mbus_bridge_end - base; in mvebu_mbus_setup_cpu_target_nooverlap()
680 size -= end - mbus_bridge_base; in mvebu_mbus_setup_cpu_target_nooverlap()
683 w->cs_index = i; in mvebu_mbus_setup_cpu_target_nooverlap()
684 w->mbus_attr = 0xf & ~(1 << i); in mvebu_mbus_setup_cpu_target_nooverlap()
685 if (mbus->hw_io_coherency) in mvebu_mbus_setup_cpu_target_nooverlap()
686 w->mbus_attr |= ATTR_HW_COHERENCY; in mvebu_mbus_setup_cpu_target_nooverlap()
687 w->base = base; in mvebu_mbus_setup_cpu_target_nooverlap()
688 w->size = size; in mvebu_mbus_setup_cpu_target_nooverlap()
704 u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i)); in mvebu_mbus_default_setup_cpu_target()
705 u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i)); in mvebu_mbus_default_setup_cpu_target()
718 w->cs_index = i; in mvebu_mbus_default_setup_cpu_target()
719 w->mbus_attr = 0xf & ~(1 << i); in mvebu_mbus_default_setup_cpu_target()
720 if (mbus->hw_io_coherency) in mvebu_mbus_default_setup_cpu_target()
721 w->mbus_attr |= ATTR_HW_COHERENCY; in mvebu_mbus_default_setup_cpu_target()
722 w->base = base & DDR_BASE_CS_LOW_MASK; in mvebu_mbus_default_setup_cpu_target()
723 w->size = (u64)(size | ~DDR_SIZE_MASK) + 1; in mvebu_mbus_default_setup_cpu_target()
736 u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i)); in mvebu_mbus_default_save_cpu_target()
737 u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i)); in mvebu_mbus_default_save_cpu_target()
739 writel(mbus->sdramwins_phys_base + DDR_BASE_CS_OFF(i), in mvebu_mbus_default_save_cpu_target()
742 writel(mbus->sdramwins_phys_base + DDR_SIZE_CS_OFF(i), in mvebu_mbus_default_save_cpu_target()
760 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i)); in mvebu_mbus_dove_setup_cpu_target()
769 w->cs_index = i; in mvebu_mbus_dove_setup_cpu_target()
770 w->mbus_attr = 0; /* CS address decoding done inside */ in mvebu_mbus_dove_setup_cpu_target()
773 w->base = map & 0xff800000; in mvebu_mbus_dove_setup_cpu_target()
774 w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4); in mvebu_mbus_dove_setup_cpu_target()
788 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i)); in mvebu_mbus_dove_save_cpu_target()
790 writel(mbus->sdramwins_phys_base + DOVE_DDR_BASE_CS_OFF(i), in mvebu_mbus_dove_save_cpu_target()
801 return mbus_state.soc->save_cpu_target(&mbus_state, store_addr); in mvebu_mbus_save_cpu_target()
874 { .compatible = "marvell,armada370-mbus",
876 { .compatible = "marvell,armada375-mbus",
878 { .compatible = "marvell,armada380-mbus",
880 { .compatible = "marvell,armadaxp-mbus",
882 { .compatible = "marvell,kirkwood-mbus",
884 { .compatible = "marvell,dove-mbus",
886 { .compatible = "marvell,orion5x-88f5281-mbus",
888 { .compatible = "marvell,orion5x-88f5182-mbus",
890 { .compatible = "marvell,orion5x-88f5181-mbus",
892 { .compatible = "marvell,orion5x-88f6183-mbus",
894 { .compatible = "marvell,mv78xx0-mbus",
912 return -EINVAL; in mvebu_mbus_add_window_remap_by_id()
960 return -ENODEV; in mvebu_mbus_get_dram_win_info()
964 for (i = 0; i < dram->num_cs; i++) { in mvebu_mbus_get_dram_win_info()
965 const struct mbus_dram_window *cs = dram->cs + i; in mvebu_mbus_get_dram_win_info()
967 if (cs->base <= phyaddr && in mvebu_mbus_get_dram_win_info()
968 phyaddr <= (cs->base + cs->size - 1)) { in mvebu_mbus_get_dram_win_info()
969 *target = dram->mbus_dram_target_id; in mvebu_mbus_get_dram_win_info()
970 *attr = cs->mbus_attr; in mvebu_mbus_get_dram_win_info()
976 return -EINVAL; in mvebu_mbus_get_dram_win_info()
985 for (win = 0; win < mbus_state.soc->num_wins; win++) { in mvebu_mbus_get_io_win_info()
999 return -EINVAL; in mvebu_mbus_get_io_win_info()
1012 if (!s->mbuswins_base) in mvebu_mbus_debugfs_init()
1015 s->debugfs_root = debugfs_create_dir("mvebu-mbus", NULL); in mvebu_mbus_debugfs_init()
1016 if (s->debugfs_root) { in mvebu_mbus_debugfs_init()
1017 s->debugfs_sdram = debugfs_create_file("sdram", S_IRUGO, in mvebu_mbus_debugfs_init()
1018 s->debugfs_root, NULL, in mvebu_mbus_debugfs_init()
1020 s->debugfs_devs = debugfs_create_file("devices", S_IRUGO, in mvebu_mbus_debugfs_init()
1021 s->debugfs_root, NULL, in mvebu_mbus_debugfs_init()
1034 if (!s->mbusbridge_base) in mvebu_mbus_suspend()
1035 return -ENODEV; in mvebu_mbus_suspend()
1037 for (win = 0; win < s->soc->num_wins; win++) { in mvebu_mbus_suspend()
1038 void __iomem *addr = s->mbuswins_base + in mvebu_mbus_suspend()
1039 s->soc->win_cfg_offset(win); in mvebu_mbus_suspend()
1042 s->wins[win].base = readl(addr + WIN_BASE_OFF); in mvebu_mbus_suspend()
1043 s->wins[win].ctrl = readl(addr + WIN_CTRL_OFF); in mvebu_mbus_suspend()
1048 addr_rmp = s->mbuswins_base + in mvebu_mbus_suspend()
1049 s->soc->win_remap_offset(win); in mvebu_mbus_suspend()
1051 s->wins[win].remap_lo = readl(addr_rmp + WIN_REMAP_LO_OFF); in mvebu_mbus_suspend()
1052 s->wins[win].remap_hi = readl(addr_rmp + WIN_REMAP_HI_OFF); in mvebu_mbus_suspend()
1055 s->mbus_bridge_ctrl = readl(s->mbusbridge_base + in mvebu_mbus_suspend()
1057 s->mbus_bridge_base = readl(s->mbusbridge_base + in mvebu_mbus_suspend()
1068 writel(s->mbus_bridge_ctrl, in mvebu_mbus_resume()
1069 s->mbusbridge_base + MBUS_BRIDGE_CTRL_OFF); in mvebu_mbus_resume()
1070 writel(s->mbus_bridge_base, in mvebu_mbus_resume()
1071 s->mbusbridge_base + MBUS_BRIDGE_BASE_OFF); in mvebu_mbus_resume()
1073 for (win = 0; win < s->soc->num_wins; win++) { in mvebu_mbus_resume()
1074 void __iomem *addr = s->mbuswins_base + in mvebu_mbus_resume()
1075 s->soc->win_cfg_offset(win); in mvebu_mbus_resume()
1078 writel(s->wins[win].base, addr + WIN_BASE_OFF); in mvebu_mbus_resume()
1079 writel(s->wins[win].ctrl, addr + WIN_CTRL_OFF); in mvebu_mbus_resume()
1084 addr_rmp = s->mbuswins_base + in mvebu_mbus_resume()
1085 s->soc->win_remap_offset(win); in mvebu_mbus_resume()
1087 writel(s->wins[win].remap_lo, addr_rmp + WIN_REMAP_LO_OFF); in mvebu_mbus_resume()
1088 writel(s->wins[win].remap_hi, addr_rmp + WIN_REMAP_HI_OFF); in mvebu_mbus_resume()
1108 mbus->mbuswins_base = ioremap(mbuswins_phys_base, mbuswins_size); in mvebu_mbus_common_init()
1109 if (!mbus->mbuswins_base) in mvebu_mbus_common_init()
1110 return -ENOMEM; in mvebu_mbus_common_init()
1112 mbus->sdramwins_base = ioremap(sdramwins_phys_base, sdramwins_size); in mvebu_mbus_common_init()
1113 if (!mbus->sdramwins_base) { in mvebu_mbus_common_init()
1115 return -ENOMEM; in mvebu_mbus_common_init()
1118 mbus->sdramwins_phys_base = sdramwins_phys_base; in mvebu_mbus_common_init()
1121 mbus->mbusbridge_base = ioremap(mbusbridge_phys_base, in mvebu_mbus_common_init()
1123 if (!mbus->mbusbridge_base) { in mvebu_mbus_common_init()
1124 iounmap(mbus->sdramwins_base); in mvebu_mbus_common_init()
1125 iounmap(mbus->mbuswins_base); in mvebu_mbus_common_init()
1126 return -ENOMEM; in mvebu_mbus_common_init()
1129 mbus->mbusbridge_base = NULL; in mvebu_mbus_common_init()
1131 for (win = 0; win < mbus->soc->num_wins; win++) in mvebu_mbus_common_init()
1134 mbus->soc->setup_cpu_target(mbus); in mvebu_mbus_common_init()
1139 mbus->mbuswins_base + UNIT_SYNC_BARRIER_OFF); in mvebu_mbus_common_init()
1153 for (of_id = of_mvebu_mbus_ids; of_id->compatible[0]; of_id++) in mvebu_mbus_init()
1154 if (!strcmp(of_id->compatible, soc)) in mvebu_mbus_init()
1157 if (!of_id->compatible[0]) { in mvebu_mbus_init()
1159 return -ENODEV; in mvebu_mbus_init()
1162 mbus_state.soc = of_id->data; in mvebu_mbus_init()
1174 * - bits 28 to 31: MBus custom field
1175 * - bits 24 to 27: window target ID
1176 * - bits 16 to 23: window attribute ID
1177 * - bits 0 to 15: unused
1190 return -EBUSY; in mbus_dt_setup_win()
1197 return -ENOMEM; in mbus_dt_setup_win()
1222 prop = of_get_property(node, "#address-cells", NULL); in mbus_parse_ranges()
1225 prop = of_get_property(node, "#size-cells", NULL); in mbus_parse_ranges()
1233 return -EINVAL; in mbus_parse_ranges()
1256 * An entry with a non-zero custom field do not in mbus_dt_setup()
1288 mem->end = -1; in mvebu_mbus_get_pcie_resources()
1290 io->end = -1; in mvebu_mbus_get_pcie_resources()
1292 ret = of_property_read_u32_array(np, "pcie-mem-aperture", reg, ARRAY_SIZE(reg)); in mvebu_mbus_get_pcie_resources()
1294 mem->start = reg[0]; in mvebu_mbus_get_pcie_resources()
1295 mem->end = mem->start + reg[1] - 1; in mvebu_mbus_get_pcie_resources()
1296 mem->flags = IORESOURCE_MEM; in mvebu_mbus_get_pcie_resources()
1299 ret = of_property_read_u32_array(np, "pcie-io-aperture", reg, ARRAY_SIZE(reg)); in mvebu_mbus_get_pcie_resources()
1301 io->start = reg[0]; in mvebu_mbus_get_pcie_resources()
1302 io->end = io->start + reg[1] - 1; in mvebu_mbus_get_pcie_resources()
1303 io->flags = IORESOURCE_IO; in mvebu_mbus_get_pcie_resources()
1318 return -ENODEV; in mvebu_mbus_dt_init()
1321 mbus_state.soc = of_id->data; in mvebu_mbus_dt_init()
1326 return -EINVAL; in mvebu_mbus_dt_init()
1331 pr_err("could not find an 'mbus-controller' node\n"); in mvebu_mbus_dt_init()
1332 return -ENODEV; in mvebu_mbus_dt_init()
1337 return -EINVAL; in mvebu_mbus_dt_init()
1342 return -EINVAL; in mvebu_mbus_dt_init()
1353 if (mbus_state.soc->has_mbus_bridge) { in mvebu_mbus_dt_init()
1355 pr_warn(FW_WARN "deprecated mbus-mvebu Device Tree, suspend/resume will not work\n"); in mvebu_mbus_dt_init()
1360 /* Get optional pcie-{mem,io}-aperture properties */ in mvebu_mbus_dt_init()