Lines Matching +full:0 +full:xaa00
69 #define swap_byte_order(x) (((x & 0xff) << 8) | ((x & 0xff00) >> 8))
84 |IF_IADBG_ABR | IF_IADBG_EVENT*/ 0;
86 module_param(IA_TX_BUF, int, 0);
87 module_param(IA_TX_BUF_SZ, int, 0);
88 module_param(IA_RX_BUF, int, 0);
89 module_param(IA_RX_BUF_SZ, int, 0);
147 tcq_wr = readl(dev->seg_reg+TCQ_WR_PTR) & 0xffff; in ia_hack_tcq()
153 *(u_short *) (dev->seg_ram + dev->host_tcq_wr) = 0; in ia_hack_tcq()
161 dev->desc_tbl[desc1 -1].timestamp = 0; in ia_hack_tcq()
162 IF_EVENT(printk("ia_hack: return_q skb = 0x%p desc = %d\n", in ia_hack_tcq()
166 if (ia_enque_rtn_q(&dev->tx_return_q, dev->desc_tbl[desc1 -1]) < 0) in ia_hack_tcq()
183 static unsigned long timer = 0; in get_desc()
189 i=0; in get_desc()
209 dev->desc_tbl[i].timestamp = 0; in get_desc()
217 return 0xFFFF; in get_desc()
227 return 0xFFFF; in get_desc()
248 foundLockUp = 0; in clear_lockup()
249 if( vcstatus->cnt == 0x05 ) { in clear_lockup()
253 if( (abr_vc->status & 0x07) == ABR_STATE /* 0x2 */ ) { in clear_lockup()
256 if ((eabr_vc->last_desc)&&((abr_vc->status & 0x07)==ABR_STATE)) in clear_lockup()
269 vcstatus->cnt = 0; in clear_lockup()
274 writew(0xFFFD, dev->seg_reg+MODE_REG_0); in clear_lockup()
277 abr_vc->status &= 0xFFF8; in clear_lockup()
278 abr_vc->status |= 0x0001; /* state is idle */ in clear_lockup()
280 for( i = 0; ((i < dev->num_vc) && (shd_tbl[i])); i++ ); in clear_lockup()
288 vcstatus->cnt = 0; in clear_lockup()
303 ** R = reserved (written as 0)
304 ** NZ = 0 if 0 cells/sec; 1 otherwise
312 #define NZ 0x4000 in cellrate_to_float()
315 #define M_MASK 0x1ff in cellrate_to_float()
316 #define E_MASK 0x1f in cellrate_to_float()
318 u32 tmp = cr & 0x00ffffff; in cellrate_to_float()
319 int i = 0; in cellrate_to_float()
320 if (cr == 0) in cellrate_to_float()
321 return 0; in cellrate_to_float()
335 #if 0
343 if ((rate & NZ) == 0)
344 return 0;
347 if (exp == 0)
363 srv_p->mcr = 0; in init_abr_vc()
364 srv_p->icr = 0x055cb7; in init_abr_vc()
365 srv_p->tbe = 0xffffff; in init_abr_vc()
366 srv_p->frtt = 0x3a; in init_abr_vc()
367 srv_p->rif = 0xf; in init_abr_vc()
368 srv_p->rdf = 0xb; in init_abr_vc()
369 srv_p->nrm = 0x4; in init_abr_vc()
370 srv_p->trm = 0x7; in init_abr_vc()
371 srv_p->cdf = 0x3; in init_abr_vc()
388 #if 0 /* sanity check */ in ia_open_abr_vc()
389 if (srv_p->pcr == 0) in ia_open_abr_vc()
411 else if (srv_p->adtf == 0) in ia_open_abr_vc()
420 memset ((caddr_t)f_abr_vc, 0, sizeof(*f_abr_vc)); in ia_open_abr_vc()
426 if ( trm == 0) trm = 1; in ia_open_abr_vc()
427 f_abr_vc->f_nrmexp =(((srv_p->nrm +1) & 0x0f) << 12)|(MRM << 8) | trm; in ia_open_abr_vc()
429 if (crm == 0) crm = 1; in ia_open_abr_vc()
430 f_abr_vc->f_crm = crm & 0xff; in ia_open_abr_vc()
437 if (adtf == 0) adtf = 1; in ia_open_abr_vc()
438 f_abr_vc->f_cdf = ((7 - srv_p->cdf) << 12 | adtf) & 0xfff; in ia_open_abr_vc()
441 f_abr_vc->f_status = 0x0042; in ia_open_abr_vc()
443 case 0: /* RFRED initialization */ in ia_open_abr_vc()
448 r_abr_vc->r_status_rdf = (15 - srv_p->rdf) & 0x000f; in ia_open_abr_vc()
450 if (air == 0) air = 1; in ia_open_abr_vc()
459 return 0; in ia_open_abr_vc()
462 u32 rateLow=0, rateHigh, rate; in ia_cbr_setup()
466 int idealSlot =0, testSlot, toBeAssigned, inc; in ia_cbr_setup()
470 u32 fracSlot = 0; in ia_cbr_setup()
471 u32 sp_mod = 0; in ia_cbr_setup()
472 u32 sp_mod2 = 0; in ia_cbr_setup()
475 if (vcc->qos.txtp.max_pcr <= 0) { in ia_cbr_setup()
481 IF_CBR(printk("CBR: CBR entries=0x%x for rate=0x%x & Gran=0x%x\n", in ia_cbr_setup()
491 IF_CBR(printk("Entries = 0x%x, CbrRemEntries = 0x%x.\n", in ia_cbr_setup()
502 cbrVC = 0; in ia_cbr_setup()
506 fracSlot = 0; in ia_cbr_setup()
508 IF_CBR(printk("Vci=0x%x,Spacing=0x%x,Sp_mod=0x%x\n",vcIndex,spacing,sp_mod);) in ia_cbr_setup()
530 inc = 0; in ia_cbr_setup()
533 IF_CBR(printk("CBR Testslot 0x%x AT Location 0x%p, NumToAssign=%d\n", in ia_cbr_setup()
540 if (testSlot < 0) { // Wrap if necessary in ia_cbr_setup()
542 IF_CBR(printk("Testslot Wrap. STable Start=0x%p,Testslot=%d\n", in ia_cbr_setup()
553 IF_CBR(printk(" Testslot=0x%x ToBeAssgned=%d\n", in ia_cbr_setup()
558 IF_CBR(printk("Reading CBR Tbl from 0x%p, CbrVal=0x%x Iteration %d\n", in ia_cbr_setup()
571 writew((CBR_EN | UBR_EN | ABR_EN | (0x23 << 2)), dev->seg_reg+STPARMS); in ia_cbr_setup()
574 return 0; in ia_cbr_setup()
578 u16 *SchedTbl, NullVci = 0; in ia_cbrVc_close()
584 if (iadev->NumEnabledCBR == 0) { in ia_cbrVc_close()
585 writew((UBR_EN | ABR_EN | (0x23 << 2)), iadev->seg_reg+STPARMS); in ia_cbrVc_close()
588 NumFound = 0; in ia_cbrVc_close()
589 for (i=0; i < iadev->CbrTotEntries; i++) in ia_cbrVc_close()
602 int tmp = 0; in ia_avail_descs()
636 return 0; in ia_que_tx()
672 if ((vcc->pop) && (skb1->len != 0)) in ia_tx_poll()
675 IF_EVENT(printk("Transmit Done - skb 0x%lx return\n", in ia_tx_poll()
687 if ((vcc->pop) && (skb->len != 0)) in ia_tx_poll()
690 IF_EVENT(printk("Tx Done - skb 0x%lx return\n",(long)skb);) in ia_tx_poll()
700 #if 0
717 for (i=15; i>=0; i--) {
718 NVRAM_CLKOUT (val & 0x8000);
751 val = 0; in ia_eeprom_get()
752 for (i=15; i>=0; i--) { in ia_eeprom_get()
798 #if 0
808 IF_INIT(printk("memType = 0x%x iadev->phy_type = 0x%x\n",
838 iadev->carrier_detect = (status & MB25_IS_GSB) ? 1 : 0;
842 iadev->carrier_detect = (status & SUNI_DS3_LOSV) ? 0 : 1;
846 iadev->carrier_detect = (status & SUNI_E3_LOS) ? 0 : 1;
849 iadev->carrier_detect = (status & SUNI_LOSV) ? 0 : 1;
858 #if 0
862 ia_phy_write32(iadev, MB25_DIAG_CONTROL, 0);
865 (ia_phy_read32(iadev, MB25_INTR_STATUS) & MB25_IS_GSB) ? 1 : 0;
885 { SUNI_DS3_FRM_INTR_ENBL, 0x17 },
886 { SUNI_DS3_FRM_CFG, 0x01 },
887 { SUNI_DS3_TRAN_CFG, 0x01 },
888 { SUNI_CONFIG, 0 },
889 { SUNI_SPLR_CFG, 0 },
890 { SUNI_SPLT_CFG, 0 }
895 iadev->carrier_detect = (status & SUNI_DS3_LOSV) ? 0 : 1;
903 { SUNI_E3_FRM_FRAM_OPTIONS, 0x04 },
904 { SUNI_E3_FRM_MAINT_OPTIONS, 0x20 },
905 { SUNI_E3_FRM_FRAM_INTR_ENBL, 0x1d },
906 { SUNI_E3_FRM_MAINT_INTR_ENBL, 0x30 },
907 { SUNI_E3_TRAN_STAT_DIAG_OPTIONS, 0 },
908 { SUNI_E3_TRAN_FRAM_OPTIONS, 0x01 },
910 { SUNI_SPLR_CFG, 0x41 },
911 { SUNI_SPLT_CFG, 0x41 }
916 iadev->carrier_detect = (status & SUNI_E3_LOS) ? 0 : 1;
924 { SUNI_INTR_ENBL, 0x28 },
926 { SUNI_ID_RESET, 0 },
928 { SUNI_MASTER_TEST, 0 },
930 { SUNI_RXCP_CTRL, 0x2c },
931 { SUNI_RXCP_FCTRL, 0x81 },
933 { SUNI_RXCP_IDLE_PAT_H1, 0 },
934 { SUNI_RXCP_IDLE_PAT_H2, 0 },
935 { SUNI_RXCP_IDLE_PAT_H3, 0 },
936 { SUNI_RXCP_IDLE_PAT_H4, 0x01 },
938 { SUNI_RXCP_IDLE_MASK_H1, 0xff },
939 { SUNI_RXCP_IDLE_MASK_H2, 0xff },
940 { SUNI_RXCP_IDLE_MASK_H3, 0xff },
941 { SUNI_RXCP_IDLE_MASK_H4, 0xfe },
943 { SUNI_RXCP_CELL_PAT_H1, 0 },
944 { SUNI_RXCP_CELL_PAT_H2, 0 },
945 { SUNI_RXCP_CELL_PAT_H3, 0 },
946 { SUNI_RXCP_CELL_PAT_H4, 0x01 },
948 { SUNI_RXCP_CELL_MASK_H1, 0xff },
949 { SUNI_RXCP_CELL_MASK_H2, 0xff },
950 { SUNI_RXCP_CELL_MASK_H3, 0xff },
951 { SUNI_RXCP_CELL_MASK_H4, 0xff },
953 { SUNI_TXCP_CTRL, 0xa4 },
954 { SUNI_TXCP_INTR_EN_STS, 0x10 },
955 { SUNI_TXCP_IDLE_PAT_H5, 0x55 }
978 static int tcnter = 0;
984 count = 0;
987 for(col = 0;count + col < length && col < 16; col++){
988 if (col != 0 && (col % 4) == 0)
993 if ((col % 4) == 0)
998 for(col = 0;count + col < length && col < 16; col++){
1032 printk("B_tcq_wr = 0x%x desc = %d last desc = %d\n",
1035 printk(" host_tcq_wr = 0x%x host_tcq_rd = 0x%x \n", iadev->host_tcq_wr,
1039 printk("tcq_st_ptr = 0x%x tcq_ed_ptr = 0x%x \n", tcq_st_ptr, tcq_ed_ptr);
1040 i = 0;
1046 for(i=0; i <iadev->num_tx_desc; i++)
1055 #if 0 /* closing the receiving size will cause too many excp int */
1062 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1065 excpq_rd_ptr = readw(iadev->reass_reg + EXCP_Q_RD_PTR) & 0xffff;
1071 error = readw(iadev->reass_ram+excpq_rd_ptr+2) & 0x0007;
1074 if (excpq_rd_ptr > (readw(iadev->reass_reg + EXCP_Q_ED_ADR)& 0xffff))
1075 excpq_rd_ptr = readw(iadev->reass_reg + EXCP_Q_ST_ADR)& 0xffff;
1077 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1107 if (iadev->rfL.pcq_rd == (readw(iadev->reass_reg+PCQ_WR_PTR)&0xffff))
1113 desc = readw(iadev->reass_ram+iadev->rfL.pcq_rd) & 0x1fff;
1114 IF_RX(printk("reass_ram = %p iadev->rfL.pcq_rd = 0x%x desc = %d\n",
1116 printk(" pcq_wr_ptr = 0x%x\n",
1117 readw(iadev->reass_reg+PCQ_WR_PTR)&0xffff);)
1132 ((buf_desc_ptr->vc_index & 0xffff) >= iadev->num_vc)) {
1137 vcc = iadev->rx_open[buf_desc_ptr->vc_index & 0xffff];
1203 out: return 0;
1216 status = readl(iadev->reass_reg+REASS_INTR_STATUS_REG) & 0xffff;
1217 IF_EVENT(printk("rx_intr: status = 0x%x\n", status);)
1226 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1231 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1240 iadev->rxing = 0;
1243 ((iadev->rx_pkt_cnt - iadev->rx_tmp_cnt) == 0)) {
1302 printk("rx_dle_intr: skb len 0\n");
1363 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1365 state = readl(iadev->reass_reg + REASS_MASK_REG) & 0xffff;
1381 if (vcc->qos.rxtp.traffic_class == ATM_NONE) return 0;
1403 ia_open_abr_vc(iadev, &srv_p, vcc, 0);
1415 return 0;
1422 unsigned long rx_pkt_start = 0;
1450 writel(iadev->rx_dle_dma & 0xfffff000,
1452 IF_INIT(printk("Tx Dle list addr: 0x%p value: 0x%0x\n",
1455 printk("Rx Dle list addr: 0x%p value: 0x%0x\n",
1459 writew(0xffff, iadev->reass_reg+REASS_MASK_REG);
1460 writew(0, iadev->reass_reg+MODE_REG);
1466 Buffer descr 0x0000 (736 - 23K)
1467 VP Table 0x5c00 (256 - 512)
1468 Except q 0x5e00 (128 - 512)
1469 Free buffer q 0x6000 (1K - 2K)
1470 Packet comp q 0x6800 (1K - 2K)
1471 Reass Table 0x7000 (1K - 2K)
1472 VC Table 0x7800 (1K - 2K)
1473 ABR VC Table 0x8000 (1K - 32K)
1484 memset_io(buf_desc_ptr, 0, sizeof(*buf_desc_ptr));
1489 memset_io(buf_desc_ptr, 0, sizeof(*buf_desc_ptr));
1491 buf_desc_ptr->buf_start_lo = rx_pkt_start & 0x0000ffff;
1495 IF_INIT(printk("Rx Buffer desc ptr: 0x%p\n", buf_desc_ptr);)
1512 IF_INIT(printk("freeq_start: 0x%p\n", freeq_start);)
1514 i = (PKT_COMP_Q * iadev->memSize) & 0xffff;
1521 i = (EXCEPTION_Q * iadev->memSize) & 0xffff;
1529 iadev->rfL.fdq_st = readw(iadev->reass_reg+FREEQ_ST_ADR) & 0xffff;
1530 iadev->rfL.fdq_ed = readw(iadev->reass_reg+FREEQ_ED_ADR) & 0xffff ;
1531 iadev->rfL.fdq_rd = readw(iadev->reass_reg+FREEQ_RD_PTR) & 0xffff;
1532 iadev->rfL.fdq_wr = readw(iadev->reass_reg+FREEQ_WR_PTR) & 0xffff;
1533 iadev->rfL.pcq_st = readw(iadev->reass_reg+PCQ_ST_ADR) & 0xffff;
1534 iadev->rfL.pcq_ed = readw(iadev->reass_reg+PCQ_ED_ADR) & 0xffff;
1535 iadev->rfL.pcq_rd = readw(iadev->reass_reg+PCQ_RD_PTR) & 0xffff;
1536 iadev->rfL.pcq_wr = readw(iadev->reass_reg+PCQ_WR_PTR) & 0xffff;
1538 IF_INIT(printk("INIT:pcq_st:0x%x pcq_ed:0x%x pcq_rd:0x%x pcq_wr:0x%x",
1543 /* writew(0x0b80, iadev->reass_reg+VP_LKUP_BASE); */
1545 - I guess we can write all 1s or 0x000f in the entire memory
1555 for(i=0; i < j; i++)
1558 vcsize_sel = 0;
1564 writew(((i>>3) & 0xfff8) | vcsize_sel, iadev->reass_reg+VC_LKUP_BASE);
1567 for(i = 0; i < j; i++)
1584 memset ((char*)abr_vc_table, 0, j * sizeof(*abr_vc_table));
1585 for(i = 0; i < j; i++) {
1586 abr_vc_table->rdf = 0x0003;
1587 abr_vc_table->air = 0x5eb1;
1594 writew(0xff00, iadev->reass_reg+VP_FILTER);
1595 writew(0, iadev->reass_reg+XTRA_RM_OFFSET);
1596 writew(0x1, iadev->reass_reg+PROTOCOL_ID);
1602 writew(0xF6F8, iadev->reass_reg+PKT_TM_CNT );
1604 i = (j >> 6) & 0xFF;
1606 i |= ((j << 2) & 0xFF00);
1610 for(i=0; i<iadev->num_tx_desc;i++)
1611 iadev->desc_tbl[i].timestamp = 0;
1630 iadev->rx_pkt_cnt = 0;
1633 return 0;
1647 Buffer descr 0x0000 (128 - 4K)
1648 UBR sched 0x1000 (1K - 4K)
1649 UBR Wait q 0x2000 (1K - 4K)
1650 Commn queues 0x3000 Packet Ready, Trasmit comp(0x3100)
1652 extended VC 0x4000 (1K - 8K)
1653 ABR sched 0x6000 and ABR wait queue (1K - 2K) each
1654 CBR sched 0x7000 (as needed)
1655 VC table 0x8000 (1K - 32K)
1726 if ((vcc->pop) && (skb->len != 0))
1738 IF_EVENT(printk("tx_dle_intr: enque skb = 0x%p \n", skb);)
1754 if (vcc->qos.txtp.traffic_class == ATM_NONE) return 0;
1768 memset((caddr_t)ia_vcc, 0, sizeof(*ia_vcc));
1777 ia_vcc->vc_desc_cnt = 0;
1783 else if ((vcc->qos.txtp.max_pcr == 0)&&( vcc->qos.txtp.pcr <= 0))
1785 else if ((vcc->qos.txtp.max_pcr > vcc->qos.txtp.pcr) && (vcc->qos.txtp.max_pcr> 0))
1800 if (vcc->qos.txtp.max_sdu != 0) {
1816 memset((caddr_t)vc, 0, sizeof(*vc));
1817 memset((caddr_t)evc, 0, sizeof(*evc));
1824 evc->atm_hdr1 = (vcc->vci >> 12) & 0x000f;
1825 evc->atm_hdr2 = (vcc->vci & 0x0fff) << 4;
1833 if (vcc->qos.txtp.pcr > 0)
1835 IF_UBR(printk("UBR: txtp.pcr = 0x%x f_rate = 0x%x\n",
1842 if (vcc->qos.txtp.pcr > 0)
1844 if (vcc->qos.txtp.min_pcr > 0) {
1851 else srv_p.mcr = 0;
1886 if ((ret = ia_cbr_setup (iadev, vcc)) < 0) {
1895 return 0;
1918 IF_INIT(printk("Tx MASK REG: 0x%0x\n",
1934 writel(iadev->tx_dle_dma & 0xfffff000,
1936 writew(0xffff, iadev->seg_reg+SEG_MASK_REG);
1937 writew(0, iadev->seg_reg+MODE_REG_0);
1946 Buffer descr 0x0000 (128 - 4K)
1947 Commn queues 0x1000 Transmit comp, Packet ready(0x1400)
1950 CBR Table 0x1800 (as needed) - 6K
1951 UBR Table 0x3000 (1K - 4K) - 12K
1952 UBR Wait queue 0x4000 (1K - 4K) - 16K
1953 ABR sched 0x5000 and ABR wait queue (1K - 2K) each
1955 extended VC 0x6000 (1K - 8K) - 24K
1956 VC Table 0x8000 (1K - 32K) - 32K
1958 Between 0x2000 (8K) and 0x3000 (12K) there is 4K space left for VBR Tbl
1967 memset((caddr_t)buf_desc_ptr, 0, sizeof(*buf_desc_ptr));
1972 memset((caddr_t)buf_desc_ptr, 0, sizeof(*buf_desc_ptr));
1975 buf_desc_ptr->buf_start_lo = tx_pkt_start & 0x0000ffff;
1986 for (i= 0; i< iadev->num_tx_desc; i++)
2038 iadev->ffL.prq_st = readw(iadev->seg_reg+PRQ_ST_ADR) & 0xffff;
2039 iadev->ffL.prq_ed = readw(iadev->seg_reg+PRQ_ED_ADR) & 0xffff;
2040 iadev->ffL.prq_wr = readw(iadev->seg_reg+PRQ_WR_PTR) & 0xffff;
2042 iadev->ffL.tcq_st = readw(iadev->seg_reg+TCQ_ST_ADR) & 0xffff;
2043 iadev->ffL.tcq_ed = readw(iadev->seg_reg+TCQ_ED_ADR) & 0xffff;
2044 iadev->ffL.tcq_rd = readw(iadev->seg_reg+TCQ_RD_PTR) & 0xffff;
2052 *prq_start = (u_short)0; /* desc 1 in all entries */
2057 #if 1 /* for 1K VC board, CBR_PTR_BASE is 0 */
2058 writew(0,iadev->seg_reg+CBR_PTR_BASE);
2061 IF_INIT(printk("cbr_ptr_base = 0x%x ", tmp16);)
2065 IF_INIT(printk("value in register = 0x%x\n",
2069 IF_INIT(printk("cbr_tab_beg = 0x%x in reg = 0x%x \n", tmp16,
2074 IF_INIT(printk("iadev->seg_reg = 0x%p CBR_PTR_BASE = 0x%x\n",
2076 IF_INIT(printk("CBR_TAB_BEG = 0x%x, CBR_TAB_END = 0x%x, CBR_PTR = 0x%x\n",
2082 0, iadev->num_vc*6);
2084 iadev->CbrEntryPt = 0;
2086 iadev->NumEnabledCBR = 0;
2089 /* initialize all bytes of UBR scheduler table and wait queue to 0
2097 vcsize_sel = 0;
2105 writew(vcsize_sel | ((i >> 8) & 0xfff8),iadev->seg_reg+VCT_BASE);
2107 writew((i >> 8) & 0xfffe, iadev->seg_reg+VCTE_BASE);
2109 writew((i & 0xffff) >> 11, iadev->seg_reg+UBR_SBPTR_BASE);
2111 writew((i >> 7) & 0xffff, iadev->seg_reg+UBRWQ_BASE);
2113 0, iadev->num_vc*8);
2114 /* ABR scheduling Table(0x5000-0x57ff) and wait queue(0x5800-0x5fff)*/
2115 /* initialize all bytes of ABR scheduler table and wait queue to 0
2123 writew((i >> 11) & 0xffff, iadev->seg_reg+ABR_SBPTR_BASE);
2125 writew((i >> 7) & 0xffff, iadev->seg_reg+ABRWQ_BASE);
2128 memset((caddr_t)(iadev->seg_ram+i), 0, iadev->num_vc*4);
2138 for(i=0; i<iadev->num_vc; i++)
2140 memset((caddr_t)vc, 0, sizeof(*vc));
2141 memset((caddr_t)evc, 0, sizeof(*evc));
2146 iadev->testTable[i]->lastTime = 0;
2147 iadev->testTable[i]->fract = 0;
2158 writew((UBR_EN | (0x23 << 2)), iadev->seg_reg+STPARMS);
2162 writew((UBR_EN | ABR_EN | (0x23 << 2)), iadev->seg_reg+STPARMS);
2165 writew(0, iadev->seg_reg+IDLEHEADHI);
2166 writew(0, iadev->seg_reg+IDLEHEADLO);
2169 writew(0xaa00, iadev->seg_reg+ABRUBR_ARB);
2171 iadev->close_pending = 0;
2184 /* Mode Register 0 */
2193 iadev->tx_pkt_cnt = 0;
2196 return 0;
2199 while (--i >= 0)
2207 while (--i >= 0) {
2227 int handled = 0;
2231 while( (status = readl(iadev->reg+IPHASE5575_BUS_STATUS_REG) & 0x7f))
2234 IF_EVENT(printk("ia_int: status = 0x%x\n", status);)
2281 IF_INIT(printk("ESI: 0x%08x%04x\n", mac1, mac2);)
2282 for (i=0; i<MAC1_LEN; i++)
2285 for (i=0; i<MAC2_LEN; i++)
2287 return 0;
2297 for(i=0; i<64; i++)
2301 writel(0, iadev->reg+IPHASE5575_EXT_RESET);
2302 for(i=0; i<64; i++)
2307 return 0;
2324 dev->ci_range.vpi_bits = 0;
2328 real_base = pci_resource_start (iadev->pci, 0);
2333 printk(KERN_ERR DEV_LABEL "(itf %d): init error 0x%x\n",
2337 IF_INIT(printk(DEV_LABEL "(itf %d): rev.%d,realbase=0x%lx,irq=%d\n",
2342 iadev->pci_map_size = pci_resource_len(iadev->pci, 0);
2344 if (iadev->pci_map_size == 0x100000){
2349 else if (iadev->pci_map_size == 0x40000) {
2354 printk("Unknown pci_map_size = 0x%x\n", iadev->pci_map_size);
2411 for (i=0; i < ESI_LEN; i++)
2421 return 0;
2427 iadev->rx_cell_cnt += readw(iadev->reass_reg+CELL_CTR0)&0xffff;
2428 iadev->rx_cell_cnt += (readw(iadev->reass_reg+CELL_CTR1) & 0xffff) << 16;
2429 iadev->drop_rxpkt += readw(iadev->reass_reg + DRP_PKT_CNTR ) & 0xffff;
2430 iadev->drop_rxcell += readw(iadev->reass_reg + ERR_CNTR) & 0xffff;
2431 iadev->tx_cell_cnt += readw(iadev->seg_reg + CELL_CTR_LO_AUTO)&0xffff;
2432 iadev->tx_cell_cnt += (readw(iadev->seg_reg+CELL_CTR_HIGH_AUTO)&0xffff)<<16;
2438 static u_char blinking[8] = {0, 0, 0, 0, 0, 0, 0, 0};
2441 for (i = 0; i < iadev_count; i++) {
2444 if (blinking[i] == 0) {
2451 blinking[i] = 0;
2482 for (i = 0; i < iadev->num_vc; i++)
2485 for (i = 0; i < iadev->num_tx_desc; i++) {
2525 "master (0x%x)\n",dev->number, error);
2571 phy = 0; /* resolve compiler complaint */
2573 if ((phy=ia_phy_get(dev,0)) == 0x30)
2574 printk("IA: pm5346,rev.%d\n",phy&0x0f);
2576 printk("IA: utopia,rev.%0x\n",phy);)
2594 return 0;
2643 if (closetime == 0)
2646 wait_event_timeout(iadev->close_wait, (ia_vcc->vc_desc_cnt <= 0), closetime);
2649 iadev->testTable[vcc->vci]->lastTime = 0;
2650 iadev->testTable[vcc->vci]->fract = 0;
2653 if (vcc->qos.txtp.min_pcr > 0)
2677 abr_vc_table->rdf = 0x0003;
2678 abr_vc_table->air = 0x5eb1;
2731 #if 0
2737 first = 0;
2742 return 0;
2748 return 0;
2765 if ((board < 0) || (board > iadev_count))
2766 board = 0;
2777 for(i=0; i<0x80; i+=2, tmps++)
2778 if(put_user((u16)(readl(iadev->seg_reg+i) & 0xffff), tmps)) return -EFAULT;
2779 ia_cmds.status = 0;
2780 ia_cmds.len = 0x80;
2785 for(i=0; i<0x80; i+=2, tmps++)
2786 if(put_user((u16)(readl(iadev->reass_reg+i) & 0xffff), tmps)) return -EFAULT;
2787 ia_cmds.status = 0;
2788 ia_cmds.len = 0x80;
2802 for (i=0; i<(sizeof (rfredn_t))/4; i++)
2803 ((u_int *)rfL)[i] = readl(iadev->reass_reg + i) & 0xffff;
2805 for (i=0; i<(sizeof (ffredn_t))/4; i++)
2806 ((u_int *)ffL)[i] = readl(iadev->seg_reg + i) & 0xffff;
2814 ia_cmds.status = 0;
2821 ia_cmds.status = 0;
2824 case 0x6:
2826 ia_cmds.status = 0;
2827 printk("skb = 0x%p\n", skb_peek(&iadev->tx_backlog));
2828 printk("rtn_q: 0x%p\n",ia_deque_rtn_q(&iadev->tx_return_q));
2831 case 0x8:
2845 ia_cmds.status = 0;
2847 case 0x9:
2855 ia_cmds.status = 0;
2858 case 0xb:
2862 case 0xa:
2865 ia_cmds.status = 0;
2871 ia_cmds.status = 0;
2880 return 0;
2901 return 0;
2910 return 0;
2918 return 0;
2926 if (desc == 0xffff)
2929 desc &= 0x1fff;
2931 if ((desc == 0) || (desc > iadev->num_tx_desc))
2939 return 0; /* return SUCCESS */
2952 IA_SKB_STATE(skb) = 0;
2976 IF_TX(printk("Sent: skb = 0x%p skb->data: 0x%p len: %d, desc: %d\n",
2978 trailer->control = 0;
2980 trailer->length = ((skb->len & 0xff) << 8) | ((skb->len & 0xff00) >> 8);
2981 trailer->crc32 = 0; /* not needed - dummy bytes */
3003 memset((caddr_t)wr_ptr, 0, sizeof(*wr_ptr));
3011 /* hw bug - DLEs of 0x2d, 0x2e, 0x2f cause DMA lockup */
3012 if ((wr_ptr->bytes >> 2) == 0xb)
3013 wr_ptr->bytes = 0x30;
3016 wr_ptr->prq_wr_ptr_data = 0;
3044 #if 0
3046 if (atomic_read(&vcc->stats->tx) % 20 == 0) {
3052 } else if ((iavcc->flow_inc < 0) && (iavcc->vc_desc_cnt < 3)) {
3055 iavcc->flow_inc = 0;
3060 return 0;
3093 return 0;
3116 if (iadev->pci_map_size == 0x40000)
3146 return 0;
3188 IF_INIT(printk("dev_id = 0x%p iadev->LineRate = %d \n", dev,
3209 return 0;
3252 { PCI_VENDOR_ID_IPHASE, 0x0008, PCI_ANY_ID, PCI_ANY_ID, },
3253 { PCI_VENDOR_ID_IPHASE, 0x0009, PCI_ANY_ID, PCI_ANY_ID, },
3254 { 0,}
3270 if (ret >= 0) {