1 // SPDX-License-Identifier: GPL-2.0-or-later
3  *  sata_qstor.c - Pacific Digital Corporation QStor SATA
11  *  as Documentation/driver-api/libata.rst
38 	/* global register offsets */
41 	QS_HCT_CTRL		= 0x00e4, /* global interrupt mask offset */
45 	/* global control bits */
46 	QS_HPHY_64BIT		= (1 << 1), /* 64-bit bus detected */
47 	QS_CNFG3_GSRST		= 0x01,     /* global chip reset */
50 	/* per-channel register offsets */
57 	QS_CCT_CTR0		= 0x0900, /* chan control-0 offset */
58 	QS_CCT_CTR1		= 0x0901, /* chan control-1 offset */
68 	/* pkt sub-field headers */
83 	board_2068_idx		= 0,	/* QStor 4-port SATA/RAID */
149 	{ PCI_VDEVICE(PDC, 0x2068), board_2068_idx },
163 	return host->iomap[QS_MMIO_BAR];  in qs_mmio_base()
173 	u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);  in qs_enter_reg_mode()
174 	struct qs_port_priv *pp = ap->private_data;  in qs_enter_reg_mode()
176 	pp->state = qs_state_mmio;  in qs_enter_reg_mode()
183 	u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);  in qs_reset_channel_logic()
192 	u8 __iomem *mmio_base = qs_mmio_base(ap->host);  in qs_freeze()
200 	u8 __iomem *mmio_base = qs_mmio_base(ap->host);  in qs_thaw()
208 	struct ata_port *ap = link->ap;  in qs_prereset()
217 		return -EINVAL;  in qs_scr_read()
218 	*val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 8));  in qs_scr_read()
231 		return -EINVAL;  in qs_scr_write()
232 	writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 8));  in qs_scr_write()
239 	struct ata_port *ap = qc->ap;  in qs_fill_sg()
240 	struct qs_port_priv *pp = ap->private_data;  in qs_fill_sg()
241 	u8 *prd = pp->pkt + QS_CPB_BYTES;  in qs_fill_sg()
244 	for_each_sg(qc->sg, sg, qc->n_elem, si) {  in qs_fill_sg()
265 	struct qs_port_priv *pp = qc->ap->private_data;  in qs_qc_prep()
266 	u8 dflags = QS_DF_PORD, *buf = pp->pkt;  in qs_qc_prep()
273 	qs_enter_reg_mode(qc->ap);  in qs_qc_prep()
274 	if (qc->tf.protocol != ATA_PROT_DMA)  in qs_qc_prep()
279 	if ((qc->tf.flags & ATA_TFLAG_WRITE))  in qs_qc_prep()
281 	if ((qc->tf.flags & ATA_TFLAG_LBA48))  in qs_qc_prep()
287 	*(__le32 *)(&buf[ 4]) = cpu_to_le32(qc->nbytes);  in qs_qc_prep()
289 	addr = ((u64)pp->pkt_dma) + QS_CPB_BYTES;  in qs_qc_prep()
297 	ata_tf_to_fis(&qc->tf, 0, 1, &buf[32]);  in qs_qc_prep()
304 	struct ata_port *ap = qc->ap;  in qs_packet_start()
305 	u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);  in qs_packet_start()
317 	struct qs_port_priv *pp = qc->ap->private_data;  in qs_qc_issue()
319 	switch (qc->tf.protocol) {  in qs_qc_issue()
321 		pp->state = qs_state_pkt;  in qs_qc_issue()
333 	pp->state = qs_state_mmio;  in qs_qc_issue()
339 	qc->err_mask |= ac_err_mask(status);  in qs_do_or_die()
341 	if (!qc->err_mask) {  in qs_do_or_die()
344 		struct ata_port    *ap  = qc->ap;  in qs_do_or_die()
345 		struct ata_eh_info *ehi = &ap->link.eh_info;  in qs_do_or_die()
350 		if (qc->err_mask == AC_ERR_DEV)  in qs_do_or_die()
373 			struct ata_port *ap = host->ports[port_no];  in qs_intr_pkt()
374 			struct qs_port_priv *pp = ap->private_data;  in qs_intr_pkt()
380 			if (!pp || pp->state != qs_state_pkt)  in qs_intr_pkt()
382 			qc = ata_qc_from_tag(ap, ap->link.active_tag);  in qs_intr_pkt()
383 			if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {  in qs_intr_pkt()
387 					qs_enter_reg_mode(qc->ap);  in qs_intr_pkt()
403 	for (port_no = 0; port_no < host->n_ports; ++port_no) {  in qs_intr_mmio()
404 		struct ata_port *ap = host->ports[port_no];  in qs_intr_mmio()
405 		struct qs_port_priv *pp = ap->private_data;  in qs_intr_mmio()
408 		qc = ata_qc_from_tag(ap, ap->link.active_tag);  in qs_intr_mmio()
424 		if (!pp || pp->state != qs_state_mmio)  in qs_intr_mmio()
426 		if (!(qc->tf.flags & ATA_TFLAG_POLLING))  in qs_intr_mmio()
440 	spin_lock_irqsave(&host->lock, flags);  in qs_intr()
442 	spin_unlock_irqrestore(&host->lock, flags);  in qs_intr()
451 	port->cmd_addr		=  in qs_ata_setup_port()
452 	port->data_addr		= base + 0x400;  in qs_ata_setup_port()
453 	port->error_addr	=  in qs_ata_setup_port()
454 	port->feature_addr	= base + 0x408; /* hob_feature = 0x409 */  in qs_ata_setup_port()
455 	port->nsect_addr	= base + 0x410; /* hob_nsect   = 0x411 */  in qs_ata_setup_port()
456 	port->lbal_addr		= base + 0x418; /* hob_lbal    = 0x419 */  in qs_ata_setup_port()
457 	port->lbam_addr		= base + 0x420; /* hob_lbam    = 0x421 */  in qs_ata_setup_port()
458 	port->lbah_addr		= base + 0x428; /* hob_lbah    = 0x429 */  in qs_ata_setup_port()
459 	port->device_addr	= base + 0x430;  in qs_ata_setup_port()
460 	port->status_addr	=  in qs_ata_setup_port()
461 	port->command_addr	= base + 0x438;  in qs_ata_setup_port()
462 	port->altstatus_addr	=  in qs_ata_setup_port()
463 	port->ctl_addr		= base + 0x440;  in qs_ata_setup_port()
464 	port->scr_addr		= base + 0xc00;  in qs_ata_setup_port()
469 	struct device *dev = ap->host->dev;  in qs_port_start()
471 	void __iomem *mmio_base = qs_mmio_base(ap->host);  in qs_port_start()
472 	void __iomem *chan = mmio_base + (ap->port_no * 0x4000);  in qs_port_start()
477 		return -ENOMEM;  in qs_port_start()
478 	pp->pkt = dmam_alloc_coherent(dev, QS_PKT_BYTES, &pp->pkt_dma,  in qs_port_start()
480 	if (!pp->pkt)  in qs_port_start()
481 		return -ENOMEM;  in qs_port_start()
482 	ap->private_data = pp;  in qs_port_start()
485 	addr = (u64)pp->pkt_dma;  in qs_port_start()
496 	writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */  in qs_host_stop()
501 	void __iomem *mmio_base = host->iomap[QS_MMIO_BAR];  in qs_host_init()
505 	writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */  in qs_host_init()
508 	for (port_no = 0; port_no < host->n_ports; ++port_no) {  in qs_host_init()
516 	for (port_no = 0; port_no < host->n_ports; ++port_no) {  in qs_host_init()
530  * The QStor understands 64-bit buses, and uses 64-bit fields
535  * If we're 32-bit limited somewhere, then our 64-bit fields will
536  * just end up with zeros in the upper 32-bits, without any special
545 	rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));  in qs_set_dma_masks()
547 		dev_err(&pdev->dev, "%d-bit DMA enable failed\n", dma_bits);  in qs_set_dma_masks()
554 	unsigned int board_idx = (unsigned int) ent->driver_data;  in qs_ata_init_one()
559 	ata_print_version_once(&pdev->dev, DRV_VERSION);  in qs_ata_init_one()
562 	host = ata_host_alloc_pinfo(&pdev->dev, ppi, QS_PORTS);  in qs_ata_init_one()
564 		return -ENOMEM;  in qs_ata_init_one()
572 		return -ENODEV;  in qs_ata_init_one()
577 	host->iomap = pcim_iomap_table(pdev);  in qs_ata_init_one()
579 	rc = qs_set_dma_masks(pdev, host->iomap[QS_MMIO_BAR]);  in qs_ata_init_one()
583 	for (port_no = 0; port_no < host->n_ports; ++port_no) {  in qs_ata_init_one()
584 		struct ata_port *ap = host->ports[port_no];  in qs_ata_init_one()
586 		void __iomem *chan = host->iomap[QS_MMIO_BAR] + offset;  in qs_ata_init_one()
588 		qs_ata_setup_port(&ap->ioaddr, chan);  in qs_ata_init_one()
590 		ata_port_pbar_desc(ap, QS_MMIO_BAR, -1, "mmio");  in qs_ata_init_one()
598 	return ata_host_activate(host, pdev->irq, qs_intr, IRQF_SHARED,  in qs_ata_init_one()
605 MODULE_DESCRIPTION("Pacific Digital Corporation QStor SATA low-level driver");