Lines Matching +full:ext +full:- +full:gen
1 // SPDX-License-Identifier: GPL-2.0-only
3 * sata_mv.c - Marvell SATA support
5 * Copyright 2008-2009: Marvell Corporation, all rights reserved.
12 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
18 * --> Develop a low-power-consumption strategy, and implement it.
20 * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds.
22 * --> [Experiment, Marvell value added] Is it possible to use target
23 * mode to cross-connect two Linux boxes with Marvell cards? If so,
31 * 80x1-B2 errata PCI#11:
34 * should be careful to insert those cards only onto PCI-X bus #0,
47 #include <linux/dma-mapping.h>
95 /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */
97 MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */
103 * Per-chip ("all ports") interrupt coalescing feature.
133 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
144 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
147 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
148 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
164 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
165 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
166 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
172 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
173 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
203 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
209 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
216 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
217 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
229 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
230 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
231 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
242 * Per-HC (Host-Controller) interrupt coalescing feature.
266 LTMODE = 0x30c, /* requires read-after-write */
272 PHY_MODE4 = 0x314, /* requires read-after-write */
311 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
312 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
322 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
323 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
325 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
397 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
425 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
438 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
439 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
440 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
441 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
442 #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
449 * we need on /length/ in mv_fill-sg().
507 * when switching between EDMA and non-EDMA modes.
556 * all the clock operations become no-ops (see clk.h).
568 * alignment for hardware-accessed data structures,
670 .can_queue = MV_MAX_Q_DEPTH - 1,
874 * This is hot-path stuff, so not a function.
918 struct mv_host_priv *hpriv = host->private_data; in mv_host_base()
919 return hpriv->base; in mv_host_base()
924 return mv_port_base(mv_host_base(ap->host), ap->port_no); in mv_ap_base()
933 * mv_save_cached_regs - (re-)initialize cached port registers
945 struct mv_port_priv *pp = ap->private_data; in mv_save_cached_regs()
947 pp->cached.fiscfg = readl(port_mmio + FISCFG); in mv_save_cached_regs()
948 pp->cached.ltmode = readl(port_mmio + LTMODE); in mv_save_cached_regs()
949 pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND); in mv_save_cached_regs()
950 pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD); in mv_save_cached_regs()
954 * mv_write_cached_reg - write to a cached port register
968 * Workaround for 88SX60x1-B2 FEr SATA#13: in mv_write_cached_reg()
969 * Read-after-write is needed to prevent generating 64-bit in mv_write_cached_reg()
974 * +1 usec read-after-write delay for unaffected registers. in mv_write_cached_reg()
997 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ in mv_set_edma_ptrs()
998 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; in mv_set_edma_ptrs()
1000 WARN_ON(pp->crqb_dma & 0x3ff); in mv_set_edma_ptrs()
1001 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI); in mv_set_edma_ptrs()
1002 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index, in mv_set_edma_ptrs()
1009 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ in mv_set_edma_ptrs()
1010 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT; in mv_set_edma_ptrs()
1012 WARN_ON(pp->crpb_dma & 0xff); in mv_set_edma_ptrs()
1013 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI); in mv_set_edma_ptrs()
1015 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index, in mv_set_edma_ptrs()
1033 writelfl(mask, hpriv->main_irq_mask_addr); in mv_write_main_irq_mask()
1039 struct mv_host_priv *hpriv = host->private_data; in mv_set_main_irq_mask()
1042 old_mask = hpriv->main_irq_mask; in mv_set_main_irq_mask()
1045 hpriv->main_irq_mask = new_mask; in mv_set_main_irq_mask()
1053 unsigned int shift, hardport, port = ap->port_no; in mv_enable_port_irqs()
1060 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits); in mv_enable_port_irqs()
1067 struct mv_host_priv *hpriv = ap->host->private_data; in mv_clear_and_enable_port_irqs()
1068 int hardport = mv_hardport_from_port(ap->port_no); in mv_clear_and_enable_port_irqs()
1070 mv_host_base(ap->host), ap->port_no); in mv_clear_and_enable_port_irqs()
1090 struct mv_host_priv *hpriv = host->private_data; in mv_set_irq_coalescing()
1091 void __iomem *mmio = hpriv->base, *hc_mmio; in mv_set_irq_coalescing()
1094 unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC; in mv_set_irq_coalescing()
1110 spin_lock_irqsave(&host->lock, flags); in mv_set_irq_coalescing()
1146 spin_unlock_irqrestore(&host->lock, flags); in mv_set_irq_coalescing()
1150 * mv_start_edma - Enable eDMA engine
1165 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { in mv_start_edma()
1166 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0); in mv_start_edma()
1170 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) { in mv_start_edma()
1171 struct mv_host_priv *hpriv = ap->host->private_data; in mv_start_edma()
1179 pp->pp_flags |= MV_PP_FLAG_EDMA_EN; in mv_start_edma()
1194 * with two drives in-use. So we use the 15msec value above in mv_wait_for_edma_empty_idle()
1207 * mv_stop_edma_engine - Disable eDMA engine
1221 for (i = 10000; i > 0; i--) { in mv_stop_edma_engine()
1227 return -EIO; in mv_stop_edma_engine()
1233 struct mv_port_priv *pp = ap->private_data; in mv_stop_edma()
1236 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) in mv_stop_edma()
1238 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; in mv_stop_edma()
1242 err = -EIO; in mv_stop_edma()
1298 DPRINTK("All registers for port(s) %u-%u:\n", start_port, in mv_dump_all_regs()
1299 num_ports > 1 ? num_ports - 1 : start_port); in mv_dump_all_regs()
1350 *val = readl(mv_ap_base(link->ap) + ofs); in mv_scr_read()
1353 return -EINVAL; in mv_scr_read()
1361 void __iomem *addr = mv_ap_base(link->ap) + ofs; in mv_scr_write()
1362 struct mv_host_priv *hpriv = link->ap->host->private_data; in mv_scr_write()
1380 if (hpriv->hp_flags & MV_HP_FIX_LP_PHY_CTL) { in mv_scr_write()
1382 mv_ap_base(link->ap) + LP_PHY_CTL; in mv_scr_write()
1402 return -EINVAL; in mv_scr_write()
1408 * Deal with Gen-II ("mv6") hardware quirks/restrictions: in mv6_dev_config()
1410 * Gen-II does not support NCQ over a port multiplier in mv6_dev_config()
1411 * (no FIS-based switching). in mv6_dev_config()
1413 if (adev->flags & ATA_DFLAG_NCQ) { in mv6_dev_config()
1414 if (sata_pmp_attached(adev->link->ap)) { in mv6_dev_config()
1415 adev->flags &= ~ATA_DFLAG_NCQ; in mv6_dev_config()
1417 "NCQ disabled for command-based switching\n"); in mv6_dev_config()
1424 struct ata_link *link = qc->dev->link; in mv_qc_defer()
1425 struct ata_port *ap = link->ap; in mv_qc_defer()
1426 struct mv_port_priv *pp = ap->private_data; in mv_qc_defer()
1430 * for NCQ and/or FIS-based switching. in mv_qc_defer()
1432 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) in mv_qc_defer()
1438 * or a non-NCQ command in NCQ mode. in mv_qc_defer()
1443 if (unlikely(ap->excl_link)) { in mv_qc_defer()
1444 if (link == ap->excl_link) { in mv_qc_defer()
1445 if (ap->nr_active_links) in mv_qc_defer()
1447 qc->flags |= ATA_QCFLAG_CLEAR_EXCL; in mv_qc_defer()
1456 if (ap->nr_active_links == 0) in mv_qc_defer()
1465 if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) && in mv_qc_defer()
1466 (pp->pp_flags & MV_PP_FLAG_NCQ_EN)) { in mv_qc_defer()
1467 if (ata_is_ncq(qc->tf.protocol)) in mv_qc_defer()
1470 ap->excl_link = link; in mv_qc_defer()
1480 struct mv_port_priv *pp = ap->private_data; in mv_config_fbs()
1483 u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg; in mv_config_fbs()
1484 u32 ltmode, *old_ltmode = &pp->cached.ltmode; in mv_config_fbs()
1485 u32 haltcond, *old_haltcond = &pp->cached.haltcond; in mv_config_fbs()
1509 struct mv_host_priv *hpriv = ap->host->private_data; in mv_60x1_errata_sata25()
1513 old = readl(hpriv->base + GPIO_PORT_CTL); in mv_60x1_errata_sata25()
1519 writel(new, hpriv->base + GPIO_PORT_CTL); in mv_60x1_errata_sata25()
1523 * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma
1528 * Bit-0 of the "EDMA RESERVED" register enables/disables use
1536 struct mv_port_priv *pp = ap->private_data; in mv_bmdma_enable_iie()
1537 u32 new, *old = &pp->cached.unknown_rsvd; in mv_bmdma_enable_iie()
1562 struct ata_host *host = ap->host; in mv_soc_led_blink_enable()
1563 struct mv_host_priv *hpriv = host->private_data; in mv_soc_led_blink_enable()
1567 if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN) in mv_soc_led_blink_enable()
1569 hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN; in mv_soc_led_blink_enable()
1570 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no); in mv_soc_led_blink_enable()
1577 struct ata_host *host = ap->host; in mv_soc_led_blink_disable()
1578 struct mv_host_priv *hpriv = host->private_data; in mv_soc_led_blink_disable()
1583 if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)) in mv_soc_led_blink_disable()
1586 /* disable led-blink only if no ports are using NCQ */ in mv_soc_led_blink_disable()
1587 for (port = 0; port < hpriv->n_ports; port++) { in mv_soc_led_blink_disable()
1588 struct ata_port *this_ap = host->ports[port]; in mv_soc_led_blink_disable()
1589 struct mv_port_priv *pp = this_ap->private_data; in mv_soc_led_blink_disable()
1591 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) in mv_soc_led_blink_disable()
1595 hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN; in mv_soc_led_blink_disable()
1596 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no); in mv_soc_led_blink_disable()
1604 struct mv_port_priv *pp = ap->private_data; in mv_edma_cfg()
1605 struct mv_host_priv *hpriv = ap->host->private_data; in mv_edma_cfg()
1608 /* set up non-NCQ EDMA configuration */ in mv_edma_cfg()
1610 pp->pp_flags &= in mv_edma_cfg()
1625 * The chip can use FBS with non-NCQ, if we allow it, in mv_edma_cfg()
1628 * So disallow non-NCQ FBS for now. in mv_edma_cfg()
1635 pp->pp_flags |= MV_PP_FLAG_FBS_EN; in mv_edma_cfg()
1636 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */ in mv_edma_cfg()
1641 cfg |= (1 << 22); /* enab 4-entry host queue cache */ in mv_edma_cfg()
1645 if (hpriv->hp_flags & MV_HP_CUT_THROUGH) in mv_edma_cfg()
1646 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */ in mv_edma_cfg()
1659 pp->pp_flags |= MV_PP_FLAG_NCQ_EN; in mv_edma_cfg()
1667 struct mv_host_priv *hpriv = ap->host->private_data; in mv_port_free_dma_mem()
1668 struct mv_port_priv *pp = ap->private_data; in mv_port_free_dma_mem()
1671 if (pp->crqb) { in mv_port_free_dma_mem()
1672 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma); in mv_port_free_dma_mem()
1673 pp->crqb = NULL; in mv_port_free_dma_mem()
1675 if (pp->crpb) { in mv_port_free_dma_mem()
1676 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma); in mv_port_free_dma_mem()
1677 pp->crpb = NULL; in mv_port_free_dma_mem()
1684 if (pp->sg_tbl[tag]) { in mv_port_free_dma_mem()
1686 dma_pool_free(hpriv->sg_tbl_pool, in mv_port_free_dma_mem()
1687 pp->sg_tbl[tag], in mv_port_free_dma_mem()
1688 pp->sg_tbl_dma[tag]); in mv_port_free_dma_mem()
1689 pp->sg_tbl[tag] = NULL; in mv_port_free_dma_mem()
1695 * mv_port_start - Port specific init/start routine.
1706 struct device *dev = ap->host->dev; in mv_port_start()
1707 struct mv_host_priv *hpriv = ap->host->private_data; in mv_port_start()
1714 return -ENOMEM; in mv_port_start()
1715 ap->private_data = pp; in mv_port_start()
1717 pp->crqb = dma_pool_zalloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma); in mv_port_start()
1718 if (!pp->crqb) in mv_port_start()
1719 return -ENOMEM; in mv_port_start()
1721 pp->crpb = dma_pool_zalloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma); in mv_port_start()
1722 if (!pp->crpb) in mv_port_start()
1726 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0) in mv_port_start()
1727 ap->flags |= ATA_FLAG_AN; in mv_port_start()
1734 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool, in mv_port_start()
1735 GFP_KERNEL, &pp->sg_tbl_dma[tag]); in mv_port_start()
1736 if (!pp->sg_tbl[tag]) in mv_port_start()
1739 pp->sg_tbl[tag] = pp->sg_tbl[0]; in mv_port_start()
1740 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0]; in mv_port_start()
1744 spin_lock_irqsave(ap->lock, flags); in mv_port_start()
1747 spin_unlock_irqrestore(ap->lock, flags); in mv_port_start()
1753 return -ENOMEM; in mv_port_start()
1757 * mv_port_stop - Port specific cleanup/stop routine.
1769 spin_lock_irqsave(ap->lock, flags); in mv_port_stop()
1772 spin_unlock_irqrestore(ap->lock, flags); in mv_port_stop()
1777 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1787 struct mv_port_priv *pp = qc->ap->private_data; in mv_fill_sg()
1792 mv_sg = pp->sg_tbl[qc->hw_tag]; in mv_fill_sg()
1793 for_each_sg(qc->sg, sg, qc->n_elem, si) { in mv_fill_sg()
1802 len = 0x10000 - offset; in mv_fill_sg()
1804 mv_sg->addr = cpu_to_le32(addr & 0xffffffff); in mv_fill_sg()
1805 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); in mv_fill_sg()
1806 mv_sg->flags_size = cpu_to_le32(len & 0xffff); in mv_fill_sg()
1807 mv_sg->reserved = 0; in mv_fill_sg()
1809 sg_len -= len; in mv_fill_sg()
1818 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); in mv_fill_sg()
1830 * mv_sff_irq_clear - Clear hardware interrupt after DMA.
1835 * after libata-sff handles the bmdma interrupts.
1843 * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA.
1855 struct scsi_cmnd *scmd = qc->scsicmd; in mv_check_atapi_dma()
1858 switch (scmd->cmnd[0]) { in mv_check_atapi_dma()
1871 return -EOPNOTSUPP; /* use PIO instead */ in mv_check_atapi_dma()
1875 * mv_bmdma_setup - Set up BMDMA transaction
1883 struct ata_port *ap = qc->ap; in mv_bmdma_setup()
1885 struct mv_port_priv *pp = ap->private_data; in mv_bmdma_setup()
1893 writel((pp->sg_tbl_dma[qc->hw_tag] >> 16) >> 16, in mv_bmdma_setup()
1895 writelfl(pp->sg_tbl_dma[qc->hw_tag], in mv_bmdma_setup()
1899 ap->ops->sff_exec_command(ap, &qc->tf); in mv_bmdma_setup()
1903 * mv_bmdma_start - Start a BMDMA transaction
1911 struct ata_port *ap = qc->ap; in mv_bmdma_start()
1913 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); in mv_bmdma_start()
1921 * mv_bmdma_stop - Stop BMDMA transfer
1940 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ in mv_bmdma_stop_ap()
1947 mv_bmdma_stop_ap(qc->ap); in mv_bmdma_stop()
1951 * mv_bmdma_status - Read BMDMA status
1981 if (ioread8(ap->ioaddr.altstatus_addr) & ATA_BUSY) in mv_bmdma_status()
1991 struct ata_taskfile *tf = &qc->tf; in mv_rw_multi_errata_sata24()
2005 if ((tf->flags & ATA_TFLAG_WRITE) && is_multi_taskfile(tf)) { in mv_rw_multi_errata_sata24()
2006 if (qc->dev->multi_count > 7) { in mv_rw_multi_errata_sata24()
2007 switch (tf->command) { in mv_rw_multi_errata_sata24()
2009 tf->command = ATA_CMD_PIO_WRITE; in mv_rw_multi_errata_sata24()
2012 tf->flags &= ~ATA_TFLAG_FUA; /* ugh */ in mv_rw_multi_errata_sata24()
2015 tf->command = ATA_CMD_PIO_WRITE_EXT; in mv_rw_multi_errata_sata24()
2023 * mv_qc_prep - Host specific command preparation.
2036 struct ata_port *ap = qc->ap; in mv_qc_prep()
2037 struct mv_port_priv *pp = ap->private_data; in mv_qc_prep()
2039 struct ata_taskfile *tf = &qc->tf; in mv_qc_prep()
2043 switch (tf->protocol) { in mv_qc_prep()
2045 if (tf->command == ATA_CMD_DSM) in mv_qc_prep()
2059 if (!(tf->flags & ATA_TFLAG_WRITE)) in mv_qc_prep()
2061 WARN_ON(MV_MAX_Q_DEPTH <= qc->hw_tag); in mv_qc_prep()
2062 flags |= qc->hw_tag << CRQB_TAG_SHIFT; in mv_qc_prep()
2063 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; in mv_qc_prep()
2066 in_index = pp->req_idx; in mv_qc_prep()
2068 pp->crqb[in_index].sg_addr = in mv_qc_prep()
2069 cpu_to_le32(pp->sg_tbl_dma[qc->hw_tag] & 0xffffffff); in mv_qc_prep()
2070 pp->crqb[in_index].sg_addr_hi = in mv_qc_prep()
2071 cpu_to_le32((pp->sg_tbl_dma[qc->hw_tag] >> 16) >> 16); in mv_qc_prep()
2072 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags); in mv_qc_prep()
2074 cw = &pp->crqb[in_index].ata_cmd[0]; in mv_qc_prep()
2076 /* Sadly, the CRQB cannot accommodate all registers--there are in mv_qc_prep()
2083 switch (tf->command) { in mv_qc_prep()
2089 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0); in mv_qc_prep()
2093 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); in mv_qc_prep()
2094 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); in mv_qc_prep()
2097 /* The only other commands EDMA supports in non-queued and in mv_qc_prep()
2098 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none in mv_qc_prep()
2103 tf->command); in mv_qc_prep()
2106 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0); in mv_qc_prep()
2107 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0); in mv_qc_prep()
2108 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0); in mv_qc_prep()
2109 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0); in mv_qc_prep()
2110 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0); in mv_qc_prep()
2111 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0); in mv_qc_prep()
2112 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0); in mv_qc_prep()
2113 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0); in mv_qc_prep()
2114 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */ in mv_qc_prep()
2116 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) in mv_qc_prep()
2124 * mv_qc_prep_iie - Host specific command preparation.
2137 struct ata_port *ap = qc->ap; in mv_qc_prep_iie()
2138 struct mv_port_priv *pp = ap->private_data; in mv_qc_prep_iie()
2140 struct ata_taskfile *tf = &qc->tf; in mv_qc_prep_iie()
2144 if ((tf->protocol != ATA_PROT_DMA) && in mv_qc_prep_iie()
2145 (tf->protocol != ATA_PROT_NCQ)) in mv_qc_prep_iie()
2147 if (tf->command == ATA_CMD_DSM) in mv_qc_prep_iie()
2150 /* Fill in Gen IIE command request block */ in mv_qc_prep_iie()
2151 if (!(tf->flags & ATA_TFLAG_WRITE)) in mv_qc_prep_iie()
2154 WARN_ON(MV_MAX_Q_DEPTH <= qc->hw_tag); in mv_qc_prep_iie()
2155 flags |= qc->hw_tag << CRQB_TAG_SHIFT; in mv_qc_prep_iie()
2156 flags |= qc->hw_tag << CRQB_HOSTQ_SHIFT; in mv_qc_prep_iie()
2157 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; in mv_qc_prep_iie()
2160 in_index = pp->req_idx; in mv_qc_prep_iie()
2162 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index]; in mv_qc_prep_iie()
2163 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->hw_tag] & 0xffffffff); in mv_qc_prep_iie()
2164 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->hw_tag] >> 16) >> 16); in mv_qc_prep_iie()
2165 crqb->flags = cpu_to_le32(flags); in mv_qc_prep_iie()
2167 crqb->ata_cmd[0] = cpu_to_le32( in mv_qc_prep_iie()
2168 (tf->command << 16) | in mv_qc_prep_iie()
2169 (tf->feature << 24) in mv_qc_prep_iie()
2171 crqb->ata_cmd[1] = cpu_to_le32( in mv_qc_prep_iie()
2172 (tf->lbal << 0) | in mv_qc_prep_iie()
2173 (tf->lbam << 8) | in mv_qc_prep_iie()
2174 (tf->lbah << 16) | in mv_qc_prep_iie()
2175 (tf->device << 24) in mv_qc_prep_iie()
2177 crqb->ata_cmd[2] = cpu_to_le32( in mv_qc_prep_iie()
2178 (tf->hob_lbal << 0) | in mv_qc_prep_iie()
2179 (tf->hob_lbam << 8) | in mv_qc_prep_iie()
2180 (tf->hob_lbah << 16) | in mv_qc_prep_iie()
2181 (tf->hob_feature << 24) in mv_qc_prep_iie()
2183 crqb->ata_cmd[3] = cpu_to_le32( in mv_qc_prep_iie()
2184 (tf->nsect << 0) | in mv_qc_prep_iie()
2185 (tf->hob_nsect << 8) in mv_qc_prep_iie()
2188 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) in mv_qc_prep_iie()
2196 * mv_sff_check_status - fetch device status, if valid
2210 u8 stat = ioread8(ap->ioaddr.status_addr); in mv_sff_check_status()
2211 struct mv_port_priv *pp = ap->private_data; in mv_sff_check_status()
2213 if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) { in mv_sff_check_status()
2215 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; in mv_sff_check_status()
2223 * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register
2225 * @nwords: number of 32-bit words in the fis
2231 int i, timeout = 200, final_word = nwords - 1; in mv_send_fis()
2242 /* Flag end-of-transmission, and then send the final word */ in mv_send_fis()
2252 } while (!(ifstat & 0x1000) && --timeout); in mv_send_fis()
2267 * mv_qc_issue_fis - Issue a command directly as a FIS
2277 * of non-data commands. So avoid sending them via this function,
2285 struct ata_port *ap = qc->ap; in mv_qc_issue_fis()
2286 struct mv_port_priv *pp = ap->private_data; in mv_qc_issue_fis()
2287 struct ata_link *link = qc->dev->link; in mv_qc_issue_fis()
2291 ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis); in mv_qc_issue_fis()
2296 switch (qc->tf.protocol) { in mv_qc_issue_fis()
2298 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY; in mv_qc_issue_fis()
2301 ap->hsm_task_state = HSM_ST_FIRST; in mv_qc_issue_fis()
2304 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY; in mv_qc_issue_fis()
2305 if (qc->tf.flags & ATA_TFLAG_WRITE) in mv_qc_issue_fis()
2306 ap->hsm_task_state = HSM_ST_FIRST; in mv_qc_issue_fis()
2308 ap->hsm_task_state = HSM_ST; in mv_qc_issue_fis()
2311 ap->hsm_task_state = HSM_ST_LAST; in mv_qc_issue_fis()
2315 if (qc->tf.flags & ATA_TFLAG_POLLING) in mv_qc_issue_fis()
2321 * mv_qc_issue - Initiate a command to the host
2335 struct ata_port *ap = qc->ap; in mv_qc_issue()
2337 struct mv_port_priv *pp = ap->private_data; in mv_qc_issue()
2341 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */ in mv_qc_issue()
2343 switch (qc->tf.protocol) { in mv_qc_issue()
2345 if (qc->tf.command == ATA_CMD_DSM) { in mv_qc_issue()
2346 if (!ap->ops->bmdma_setup) /* no bmdma on GEN_I */ in mv_qc_issue()
2352 mv_start_edma(ap, port_mmio, pp, qc->tf.protocol); in mv_qc_issue()
2353 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK; in mv_qc_issue()
2354 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; in mv_qc_issue()
2357 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index, in mv_qc_issue()
2373 if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) { in mv_qc_issue()
2374 --limit_warnings; in mv_qc_issue()
2375 ata_link_warn(qc->dev->link, DRV_NAME in mv_qc_issue()
2383 if (ap->flags & ATA_FLAG_PIO_POLLING) in mv_qc_issue()
2384 qc->tf.flags |= ATA_TFLAG_POLLING; in mv_qc_issue()
2388 if (qc->tf.flags & ATA_TFLAG_POLLING) in mv_qc_issue()
2394 * We're about to send a non-EDMA capable command to the in mv_qc_issue()
2400 mv_pmp_select(ap, qc->dev->link->pmp); in mv_qc_issue()
2402 if (qc->tf.command == ATA_CMD_READ_LOG_EXT) { in mv_qc_issue()
2403 struct mv_host_priv *hpriv = ap->host->private_data; in mv_qc_issue()
2408 * from libata-eh *must* use mv_qc_issue_fis(). in mv_qc_issue()
2411 * Rather than special-case it, we'll just *always* in mv_qc_issue()
2423 struct mv_port_priv *pp = ap->private_data; in mv_get_active_qc()
2426 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) in mv_get_active_qc()
2428 qc = ata_qc_from_tag(ap, ap->link.active_tag); in mv_get_active_qc()
2429 if (qc && !(qc->tf.flags & ATA_TFLAG_POLLING)) in mv_get_active_qc()
2437 struct mv_port_priv *pp = ap->private_data; in mv_pmp_error_handler()
2439 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) { in mv_pmp_error_handler()
2446 pmp_map = pp->delayed_eh_pmp_map; in mv_pmp_error_handler()
2447 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH; in mv_pmp_error_handler()
2451 struct ata_link *link = &ap->pmp_link[pmp]; in mv_pmp_error_handler()
2478 struct ata_link *link = &ap->pmp_link[pmp]; in mv_pmp_eh_prep()
2479 struct ata_eh_info *ehi = &link->eh_info; in mv_pmp_eh_prep()
2484 ehi->err_mask |= AC_ERR_DEV; in mv_pmp_eh_prep()
2485 ehi->action |= ATA_EH_RESET; in mv_pmp_eh_prep()
2505 struct mv_port_priv *pp = ap->private_data; in mv_handle_fbs_ncq_dev_err()
2514 * Perform the post-mortem/EH only when all responses are complete. in mv_handle_fbs_ncq_dev_err()
2517 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) { in mv_handle_fbs_ncq_dev_err()
2518 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH; in mv_handle_fbs_ncq_dev_err()
2519 pp->delayed_eh_pmp_map = 0; in mv_handle_fbs_ncq_dev_err()
2521 old_map = pp->delayed_eh_pmp_map; in mv_handle_fbs_ncq_dev_err()
2525 pp->delayed_eh_pmp_map = new_map; in mv_handle_fbs_ncq_dev_err()
2532 __func__, pp->delayed_eh_pmp_map, in mv_handle_fbs_ncq_dev_err()
2533 ap->qc_active, failed_links, in mv_handle_fbs_ncq_dev_err()
2534 ap->nr_active_links); in mv_handle_fbs_ncq_dev_err()
2536 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) { in mv_handle_fbs_ncq_dev_err()
2552 * FBS+non-NCQ operation is not yet implemented. in mv_handle_fbs_non_ncq_dev_err()
2555 * Device error during FBS+non-NCQ operation: in mv_handle_fbs_non_ncq_dev_err()
2565 struct mv_port_priv *pp = ap->private_data; in mv_handle_dev_err()
2567 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) in mv_handle_dev_err()
2569 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN)) in mv_handle_dev_err()
2578 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) { in mv_handle_dev_err()
2580 * EDMA should NOT have self-disabled for this case. in mv_handle_dev_err()
2586 __func__, edma_err_cause, pp->pp_flags); in mv_handle_dev_err()
2592 * EDMA should have self-disabled for this case. in mv_handle_dev_err()
2598 __func__, edma_err_cause, pp->pp_flags); in mv_handle_dev_err()
2608 struct ata_eh_info *ehi = &ap->link.eh_info; in mv_unexpected_intr()
2615 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); in mv_unexpected_intr()
2616 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING)) in mv_unexpected_intr()
2620 ehi->err_mask |= AC_ERR_OTHER; in mv_unexpected_intr()
2621 ehi->action |= ATA_EH_RESET; in mv_unexpected_intr()
2626 * mv_err_intr - Handle error interrupts on the port
2641 struct mv_port_priv *pp = ap->private_data; in mv_err_intr()
2642 struct mv_host_priv *hpriv = ap->host->private_data; in mv_err_intr()
2644 struct ata_eh_info *ehi = &ap->link.eh_info; in mv_err_intr()
2653 sata_scr_read(&ap->link, SCR_ERROR, &serr); in mv_err_intr()
2654 sata_scr_write_flush(&ap->link, SCR_ERROR, serr); in mv_err_intr()
2665 * Device errors during FIS-based switching operation in mv_err_intr()
2675 edma_err_cause, pp->pp_flags); in mv_err_intr()
2711 * Gen-I has a different SELF_DIS bit, in mv_err_intr()
2717 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; in mv_err_intr()
2718 ata_ehi_push_desc(ehi, "EDMA self-disable"); in mv_err_intr()
2723 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; in mv_err_intr()
2724 ata_ehi_push_desc(ehi, "EDMA self-disable"); in mv_err_intr()
2738 ehi->serror |= serr; in mv_err_intr()
2739 ehi->action |= action; in mv_err_intr()
2742 qc->err_mask |= err_mask; in mv_err_intr()
2744 ehi->err_mask |= err_mask; in mv_err_intr()
2765 ata_link_abort(qc->dev->link); in mv_err_intr()
2775 u16 edma_status = le16_to_cpu(response->flags); in mv_process_crpb_response()
2779 * LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only). in mv_process_crpb_response()
2802 struct mv_host_priv *hpriv = ap->host->private_data; in mv_process_crpb_entries()
2806 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN); in mv_process_crpb_entries()
2813 while (in_index != pp->resp_idx) { in mv_process_crpb_entries()
2815 struct mv_crpb *response = &pp->crpb[pp->resp_idx]; in mv_process_crpb_entries()
2817 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK; in mv_process_crpb_entries()
2821 tag = ap->link.active_tag; in mv_process_crpb_entries()
2823 /* Gen II/IIE: get command tag from CRPB entry */ in mv_process_crpb_entries()
2824 tag = le16_to_cpu(response->id) & 0x1f; in mv_process_crpb_entries()
2835 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | in mv_process_crpb_entries()
2836 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT), in mv_process_crpb_entries()
2851 pp = ap->private_data; in mv_port_intr()
2852 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN); in mv_port_intr()
2858 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) in mv_port_intr()
2862 * Handle chip-reported errors, or continue on to handle PIO. in mv_port_intr()
2876 * mv_host_intr - Handle all interrupts on the given host controller
2885 struct mv_host_priv *hpriv = host->private_data; in mv_host_intr()
2886 void __iomem *mmio = hpriv->base, *hc_mmio; in mv_host_intr()
2893 for (port = 0; port < hpriv->n_ports; port++) { in mv_host_intr()
2894 struct ata_port *ap = host->ports[port]; in mv_host_intr()
2909 port += MV_PORTS_PER_HC - 1; in mv_host_intr()
2928 if ((port + p) >= hpriv->n_ports) in mv_host_intr()
2950 struct mv_host_priv *hpriv = host->private_data; in mv_pci_error()
2957 err_cause = readl(mmio + hpriv->irq_cause_offset); in mv_pci_error()
2959 dev_err(host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", err_cause); in mv_pci_error()
2962 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev)); in mv_pci_error()
2964 writelfl(0, mmio + hpriv->irq_cause_offset); in mv_pci_error()
2966 for (i = 0; i < host->n_ports; i++) { in mv_pci_error()
2967 ap = host->ports[i]; in mv_pci_error()
2968 if (!ata_link_offline(&ap->link)) { in mv_pci_error()
2969 ehi = &ap->link.eh_info; in mv_pci_error()
2975 ehi->action = ATA_EH_RESET; in mv_pci_error()
2976 qc = ata_qc_from_tag(ap, ap->link.active_tag); in mv_pci_error()
2978 qc->err_mask |= err_mask; in mv_pci_error()
2980 ehi->err_mask |= err_mask; in mv_pci_error()
2989 * mv_interrupt - Main interrupt event handler
3005 struct mv_host_priv *hpriv = host->private_data; in mv_interrupt()
3007 int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI; in mv_interrupt()
3010 spin_lock(&host->lock); in mv_interrupt()
3016 main_irq_cause = readl(hpriv->main_irq_cause_addr); in mv_interrupt()
3017 pending_irqs = main_irq_cause & hpriv->main_irq_mask; in mv_interrupt()
3024 handled = mv_pci_error(host, hpriv->base); in mv_interrupt()
3031 mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv); in mv_interrupt()
3033 spin_unlock(&host->lock); in mv_interrupt()
3057 struct mv_host_priv *hpriv = link->ap->host->private_data; in mv5_scr_read()
3058 void __iomem *mmio = hpriv->base; in mv5_scr_read()
3059 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no); in mv5_scr_read()
3066 return -EINVAL; in mv5_scr_read()
3071 struct mv_host_priv *hpriv = link->ap->host->private_data; in mv5_scr_write()
3072 void __iomem *mmio = hpriv->base; in mv5_scr_write()
3073 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no); in mv5_scr_write()
3080 return -EINVAL; in mv5_scr_write()
3085 struct pci_dev *pdev = to_pci_dev(host->dev); in mv5_reset_bus()
3088 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0); in mv5_reset_bus()
3112 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */ in mv5_read_preamp()
3113 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */ in mv5_read_preamp()
3135 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); in mv5_phy_errata()
3150 tmp |= hpriv->signal[port].pre; in mv5_phy_errata()
3151 tmp |= hpriv->signal[port].amps; in mv5_phy_errata()
3220 struct mv_host_priv *hpriv = host->private_data; in mv_reset_pci_bus()
3231 ZERO(hpriv->irq_cause_offset); in mv_reset_pci_bus()
3232 ZERO(hpriv->irq_mask_offset); in mv_reset_pci_bus()
3253 * mv6_reset_hc - Perform the 6xxx global soft reset
3292 } while (!(GLOB_SFT_RST & t) && (i-- > 0)); in mv6_reset_hc()
3306 } while ((GLOB_SFT_RST & t) && (i-- > 0)); in mv6_reset_hc()
3324 hpriv->signal[idx].amps = 0x7 << 8; in mv6_read_preamp()
3325 hpriv->signal[idx].pre = 0x1 << 5; in mv6_read_preamp()
3332 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ in mv6_read_preamp()
3333 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ in mv6_read_preamp()
3346 u32 hp_flags = hpriv->hp_flags; in mv6_phy_errata()
3369 * Gen-II/IIe PHY_MODE3 errata RM#2: in mv6_phy_errata()
3375 /* Guideline 88F5182 (GL# SATA-S11) */ in mv6_phy_errata()
3382 * Enforce reserved-bit restrictions on GenIIe devices only. in mv6_phy_errata()
3393 * Workaround for 60x1-B2 errata SATA#13: in mv6_phy_errata()
3400 /* Revert values of pre-emphasis and signal amps to the saved ones */ in mv6_phy_errata()
3404 m2 |= hpriv->signal[port].amps; in mv6_phy_errata()
3405 m2 |= hpriv->signal[port].pre; in mv6_phy_errata()
3434 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ in mv_soc_read_preamp()
3435 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ in mv_soc_read_preamp()
3483 for (port = 0; port < hpriv->n_ports; port++) in mv_soc_reset_hc()
3534 * soc_is_65 - check if the soc is 65 nano device
3537 * register, this register should contain non-zero value and it exists only
3542 void __iomem *port0_mmio = mv_port_base(hpriv->base, 0); in soc_is_65n()
3585 hpriv->ops->phy_errata(hpriv, mmio, port_no); in mv_reset_channel()
3608 mv_pmp_select(link->ap, sata_srst_pmp(link)); in mv_pmp_hardreset()
3615 mv_pmp_select(link->ap, sata_srst_pmp(link)); in mv_softreset()
3622 struct ata_port *ap = link->ap; in mv_hardreset()
3623 struct mv_host_priv *hpriv = ap->host->private_data; in mv_hardreset()
3624 struct mv_port_priv *pp = ap->private_data; in mv_hardreset()
3625 void __iomem *mmio = hpriv->base; in mv_hardreset()
3630 mv_reset_channel(hpriv, mmio, ap->port_no); in mv_hardreset()
3631 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; in mv_hardreset()
3632 pp->pp_flags &= in mv_hardreset()
3638 sata_ehc_deb_timing(&link->eh_context); in mv_hardreset()
3642 rc = online ? -EAGAIN : rc; in mv_hardreset()
3667 struct mv_host_priv *hpriv = ap->host->private_data; in mv_eh_thaw()
3668 unsigned int port = ap->port_no; in mv_eh_thaw()
3670 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port); in mv_eh_thaw()
3685 * mv_port_init - Perform some early initialization on a single port.
3702 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); in mv_port_init()
3703 port->error_addr = in mv_port_init()
3704 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); in mv_port_init()
3705 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); in mv_port_init()
3706 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); in mv_port_init()
3707 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); in mv_port_init()
3708 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); in mv_port_init()
3709 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); in mv_port_init()
3710 port->status_addr = in mv_port_init()
3711 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); in mv_port_init()
3713 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST; in mv_port_init()
3720 /* unmask all non-transient EDMA error interrupts */ in mv_port_init()
3731 struct mv_host_priv *hpriv = host->private_data; in mv_in_pcix_mode()
3732 void __iomem *mmio = hpriv->base; in mv_in_pcix_mode()
3736 return 0; /* not PCI-X capable */ in mv_in_pcix_mode()
3740 return 1; /* chip is in PCI-X mode */ in mv_in_pcix_mode()
3745 struct mv_host_priv *hpriv = host->private_data; in mv_pci_cut_through_okay()
3746 void __iomem *mmio = hpriv->base; in mv_pci_cut_through_okay()
3759 struct mv_host_priv *hpriv = host->private_data; in mv_60x1b2_errata_pci7()
3760 void __iomem *mmio = hpriv->base; in mv_60x1b2_errata_pci7()
3762 /* workaround for 60x1-B2 errata PCI#7 */ in mv_60x1b2_errata_pci7()
3771 struct pci_dev *pdev = to_pci_dev(host->dev); in mv_chip_id()
3772 struct mv_host_priv *hpriv = host->private_data; in mv_chip_id()
3773 u32 hp_flags = hpriv->hp_flags; in mv_chip_id()
3777 hpriv->ops = &mv5xxx_ops; in mv_chip_id()
3780 switch (pdev->revision) { in mv_chip_id()
3788 dev_warn(&pdev->dev, in mv_chip_id()
3797 hpriv->ops = &mv5xxx_ops; in mv_chip_id()
3800 switch (pdev->revision) { in mv_chip_id()
3808 dev_warn(&pdev->dev, in mv_chip_id()
3817 hpriv->ops = &mv6xxx_ops; in mv_chip_id()
3820 switch (pdev->revision) { in mv_chip_id()
3829 dev_warn(&pdev->dev, in mv_chip_id()
3838 if (pdev->vendor == PCI_VENDOR_ID_TTI && in mv_chip_id()
3839 (pdev->device == 0x2300 || pdev->device == 0x2310)) in mv_chip_id()
3854 * RAID metadata is at: (dev->n_sectors & ~0xfffff) in mv_chip_id()
3863 " use sectors 8-9 on \"Legacy\" drives," in mv_chip_id()
3869 hpriv->ops = &mv6xxx_ops; in mv_chip_id()
3874 switch (pdev->revision) { in mv_chip_id()
3879 dev_warn(&pdev->dev, in mv_chip_id()
3887 hpriv->ops = &mv_soc_65n_ops; in mv_chip_id()
3889 hpriv->ops = &mv_soc_ops; in mv_chip_id()
3895 dev_err(host->dev, "BUG: invalid board index %u\n", board_idx); in mv_chip_id()
3899 hpriv->hp_flags = hp_flags; in mv_chip_id()
3901 hpriv->irq_cause_offset = PCIE_IRQ_CAUSE; in mv_chip_id()
3902 hpriv->irq_mask_offset = PCIE_IRQ_MASK; in mv_chip_id()
3903 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS; in mv_chip_id()
3905 hpriv->irq_cause_offset = PCI_IRQ_CAUSE; in mv_chip_id()
3906 hpriv->irq_mask_offset = PCI_IRQ_MASK; in mv_chip_id()
3907 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS; in mv_chip_id()
3914 * mv_init_host - Perform some early initialization of the host.
3926 struct mv_host_priv *hpriv = host->private_data; in mv_init_host()
3927 void __iomem *mmio = hpriv->base; in mv_init_host()
3929 rc = mv_chip_id(host, hpriv->board_idx); in mv_init_host()
3934 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE; in mv_init_host()
3935 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK; in mv_init_host()
3937 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE; in mv_init_host()
3938 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK; in mv_init_host()
3942 hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr); in mv_init_host()
3947 n_hc = mv_get_hc_count(host->ports[0]->flags); in mv_init_host()
3949 for (port = 0; port < host->n_ports; port++) in mv_init_host()
3950 if (hpriv->ops->read_preamp) in mv_init_host()
3951 hpriv->ops->read_preamp(hpriv, port, mmio); in mv_init_host()
3953 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc); in mv_init_host()
3957 hpriv->ops->reset_flash(hpriv, mmio); in mv_init_host()
3958 hpriv->ops->reset_bus(host, mmio); in mv_init_host()
3959 hpriv->ops->enable_leds(hpriv, mmio); in mv_init_host()
3961 for (port = 0; port < host->n_ports; port++) { in mv_init_host()
3962 struct ata_port *ap = host->ports[port]; in mv_init_host()
3965 mv_port_init(&ap->ioaddr, port_mmio); in mv_init_host()
3982 writelfl(0, mmio + hpriv->irq_cause_offset); in mv_init_host()
3985 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset); in mv_init_host()
3990 * The per-port interrupts get done later as ports are set up. in mv_init_host()
4001 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ, in mv_create_dma_pools()
4003 if (!hpriv->crqb_pool) in mv_create_dma_pools()
4004 return -ENOMEM; in mv_create_dma_pools()
4006 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ, in mv_create_dma_pools()
4008 if (!hpriv->crpb_pool) in mv_create_dma_pools()
4009 return -ENOMEM; in mv_create_dma_pools()
4011 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ, in mv_create_dma_pools()
4013 if (!hpriv->sg_tbl_pool) in mv_create_dma_pools()
4014 return -ENOMEM; in mv_create_dma_pools()
4025 writel(0, hpriv->base + WINDOW_CTRL(i)); in mv_conf_mbus_windows()
4026 writel(0, hpriv->base + WINDOW_BASE(i)); in mv_conf_mbus_windows()
4029 for (i = 0; i < dram->num_cs; i++) { in mv_conf_mbus_windows()
4030 const struct mbus_dram_window *cs = dram->cs + i; in mv_conf_mbus_windows()
4032 writel(((cs->size - 1) & 0xffff0000) | in mv_conf_mbus_windows()
4033 (cs->mbus_attr << 8) | in mv_conf_mbus_windows()
4034 (dram->mbus_dram_target_id << 4) | 1, in mv_conf_mbus_windows()
4035 hpriv->base + WINDOW_CTRL(i)); in mv_conf_mbus_windows()
4036 writel(cs->base, hpriv->base + WINDOW_BASE(i)); in mv_conf_mbus_windows()
4041 * mv_platform_probe - handle a positive probe of an soc Marvell
4061 ata_print_version_once(&pdev->dev, DRV_VERSION); in mv_platform_probe()
4066 if (unlikely(pdev->num_resources != 2)) { in mv_platform_probe()
4067 dev_err(&pdev->dev, "invalid number of resources\n"); in mv_platform_probe()
4068 return -EINVAL; in mv_platform_probe()
4076 return -EINVAL; in mv_platform_probe()
4079 if (pdev->dev.of_node) { in mv_platform_probe()
4080 rc = of_property_read_u32(pdev->dev.of_node, "nr-ports", in mv_platform_probe()
4083 dev_err(&pdev->dev, in mv_platform_probe()
4084 "error parsing nr-ports property: %d\n", rc); in mv_platform_probe()
4089 dev_err(&pdev->dev, "nr-ports must be positive: %d\n", in mv_platform_probe()
4091 return -EINVAL; in mv_platform_probe()
4094 irq = irq_of_parse_and_map(pdev->dev.of_node, 0); in mv_platform_probe()
4096 mv_platform_data = dev_get_platdata(&pdev->dev); in mv_platform_probe()
4097 n_ports = mv_platform_data->n_ports; in mv_platform_probe()
4101 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); in mv_platform_probe()
4102 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); in mv_platform_probe()
4105 return -ENOMEM; in mv_platform_probe()
4106 hpriv->port_clks = devm_kcalloc(&pdev->dev, in mv_platform_probe()
4109 if (!hpriv->port_clks) in mv_platform_probe()
4110 return -ENOMEM; in mv_platform_probe()
4111 hpriv->port_phys = devm_kcalloc(&pdev->dev, in mv_platform_probe()
4114 if (!hpriv->port_phys) in mv_platform_probe()
4115 return -ENOMEM; in mv_platform_probe()
4116 host->private_data = hpriv; in mv_platform_probe()
4117 hpriv->board_idx = chip_soc; in mv_platform_probe()
4119 host->iomap = NULL; in mv_platform_probe()
4120 hpriv->base = devm_ioremap(&pdev->dev, res->start, in mv_platform_probe()
4122 if (!hpriv->base) in mv_platform_probe()
4123 return -ENOMEM; in mv_platform_probe()
4125 hpriv->base -= SATAHC0_REG_BASE; in mv_platform_probe()
4127 hpriv->clk = clk_get(&pdev->dev, NULL); in mv_platform_probe()
4128 if (IS_ERR(hpriv->clk)) in mv_platform_probe()
4129 dev_notice(&pdev->dev, "cannot get optional clkdev\n"); in mv_platform_probe()
4131 clk_prepare_enable(hpriv->clk); in mv_platform_probe()
4136 hpriv->port_clks[port] = clk_get(&pdev->dev, port_number); in mv_platform_probe()
4137 if (!IS_ERR(hpriv->port_clks[port])) in mv_platform_probe()
4138 clk_prepare_enable(hpriv->port_clks[port]); in mv_platform_probe()
4141 hpriv->port_phys[port] = devm_phy_optional_get(&pdev->dev, in mv_platform_probe()
4143 if (IS_ERR(hpriv->port_phys[port])) { in mv_platform_probe()
4144 rc = PTR_ERR(hpriv->port_phys[port]); in mv_platform_probe()
4145 hpriv->port_phys[port] = NULL; in mv_platform_probe()
4146 if (rc != -EPROBE_DEFER) in mv_platform_probe()
4147 dev_warn(&pdev->dev, "error getting phy %d", rc); in mv_platform_probe()
4150 hpriv->n_ports = port; in mv_platform_probe()
4153 phy_power_on(hpriv->port_phys[port]); in mv_platform_probe()
4157 hpriv->n_ports = n_ports; in mv_platform_probe()
4160 * (Re-)program MBUS remapping windows if we are asked to. in mv_platform_probe()
4166 rc = mv_create_dma_pools(hpriv, &pdev->dev); in mv_platform_probe()
4174 if (pdev->dev.of_node && in mv_platform_probe()
4175 of_device_is_compatible(pdev->dev.of_node, in mv_platform_probe()
4176 "marvell,armada-370-sata")) in mv_platform_probe()
4177 hpriv->hp_flags |= MV_HP_FIX_LP_PHY_CTL; in mv_platform_probe()
4184 dev_info(&pdev->dev, "slots %u ports %d\n", in mv_platform_probe()
4185 (unsigned)MV_MAX_Q_DEPTH, host->n_ports); in mv_platform_probe()
4192 if (!IS_ERR(hpriv->clk)) { in mv_platform_probe()
4193 clk_disable_unprepare(hpriv->clk); in mv_platform_probe()
4194 clk_put(hpriv->clk); in mv_platform_probe()
4196 for (port = 0; port < hpriv->n_ports; port++) { in mv_platform_probe()
4197 if (!IS_ERR(hpriv->port_clks[port])) { in mv_platform_probe()
4198 clk_disable_unprepare(hpriv->port_clks[port]); in mv_platform_probe()
4199 clk_put(hpriv->port_clks[port]); in mv_platform_probe()
4201 phy_power_off(hpriv->port_phys[port]); in mv_platform_probe()
4209 * mv_platform_remove - unplug a platform interface
4218 struct mv_host_priv *hpriv = host->private_data; in mv_platform_remove()
4222 if (!IS_ERR(hpriv->clk)) { in mv_platform_remove()
4223 clk_disable_unprepare(hpriv->clk); in mv_platform_remove()
4224 clk_put(hpriv->clk); in mv_platform_remove()
4226 for (port = 0; port < host->n_ports; port++) { in mv_platform_remove()
4227 if (!IS_ERR(hpriv->port_clks[port])) { in mv_platform_remove()
4228 clk_disable_unprepare(hpriv->port_clks[port]); in mv_platform_remove()
4229 clk_put(hpriv->port_clks[port]); in mv_platform_remove()
4231 phy_power_off(hpriv->port_phys[port]); in mv_platform_remove()
4253 struct mv_host_priv *hpriv = host->private_data; in mv_platform_resume()
4256 * (Re-)program MBUS remapping windows if we are asked to. in mv_platform_resume()
4280 { .compatible = "marvell,armada-370-sata", },
4281 { .compatible = "marvell,orion-sata", },
4320 * mv_print_info - Dump key info to kernel log for perusal.
4330 struct pci_dev *pdev = to_pci_dev(host->dev); in mv_print_info()
4331 struct mv_host_priv *hpriv = host->private_data; in mv_print_info()
4333 const char *scc_s, *gen; in mv_print_info() local
4347 gen = "I"; in mv_print_info()
4349 gen = "II"; in mv_print_info()
4351 gen = "IIE"; in mv_print_info()
4353 gen = "?"; in mv_print_info()
4355 dev_info(&pdev->dev, "Gen-%s %u slots %u ports %s mode IRQ via %s\n", in mv_print_info()
4356 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports, in mv_print_info()
4357 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); in mv_print_info()
4361 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
4371 unsigned int board_idx = (unsigned int)ent->driver_data; in mv_pci_init_one()
4377 ata_print_version_once(&pdev->dev, DRV_VERSION); in mv_pci_init_one()
4380 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC; in mv_pci_init_one()
4382 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); in mv_pci_init_one()
4383 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); in mv_pci_init_one()
4385 return -ENOMEM; in mv_pci_init_one()
4386 host->private_data = hpriv; in mv_pci_init_one()
4387 hpriv->n_ports = n_ports; in mv_pci_init_one()
4388 hpriv->board_idx = board_idx; in mv_pci_init_one()
4396 if (rc == -EBUSY) in mv_pci_init_one()
4400 host->iomap = pcim_iomap_table(pdev); in mv_pci_init_one()
4401 hpriv->base = host->iomap[MV_PRIMARY_BAR]; in mv_pci_init_one()
4403 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); in mv_pci_init_one()
4405 dev_err(&pdev->dev, "DMA enable failed\n"); in mv_pci_init_one()
4409 rc = mv_create_dma_pools(hpriv, &pdev->dev); in mv_pci_init_one()
4413 for (port = 0; port < host->n_ports; port++) { in mv_pci_init_one()
4414 struct ata_port *ap = host->ports[port]; in mv_pci_init_one()
4415 void __iomem *port_mmio = mv_port_base(hpriv->base, port); in mv_pci_init_one()
4416 unsigned int offset = port_mmio - hpriv->base; in mv_pci_init_one()
4418 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio"); in mv_pci_init_one()
4427 /* Enable message-switched interrupts, if requested */ in mv_pci_init_one()
4429 hpriv->hp_flags |= MV_HP_FLAG_MSI; in mv_pci_init_one()
4436 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED, in mv_pci_init_one()
4464 int rc = -ENODEV; in mv_init()
4488 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");