8  * Copyright (C) 2005 - 2012 Cavium Inc.
30  * -- 8  bits no irq, no DMA
31  * -- 16 bits no irq, no DMA
32  * -- 16 bits True IDE mode with DMA, but no irq.
131 	struct octeon_cf_port *cf_port = ap->private_data;  in octeon_cf_set_piomode()
144 	 * A divisor value of four will overflow the timing fields at  in octeon_cf_set_piomode()
153 	BUG_ON(ata_timing_compute(dev, dev->pio_mode, &timing, T, T));  in octeon_cf_set_piomode()
157 		t2--;  in octeon_cf_set_piomode()
161 		trh--;  in octeon_cf_set_piomode()
163 	pause = (int)timing.cycle - (int)timing.active -  in octeon_cf_set_piomode()
164 		(int)timing.setup - trh;  in octeon_cf_set_piomode()
168 		pause--;  in octeon_cf_set_piomode()
170 	octeon_cf_set_boot_reg_cfg(cf_port->cs0, div);  in octeon_cf_set_piomode()
171 	if (cf_port->is_true_ide)  in octeon_cf_set_piomode()
173 		octeon_cf_set_boot_reg_cfg(cf_port->cs1, div);  in octeon_cf_set_piomode()
178 	reg_tim.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs0));  in octeon_cf_set_piomode()
193 	/* How long to hold after a write to de-assert CE. */  in octeon_cf_set_piomode()
195 	/* How long to wait after a read to de-assert CE. */  in octeon_cf_set_piomode()
207 	cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs0), reg_tim.u64);  in octeon_cf_set_piomode()
208 	if (cf_port->is_true_ide)  in octeon_cf_set_piomode()
210 		cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs1),  in octeon_cf_set_piomode()
216 	struct octeon_cf_port *cf_port = ap->private_data;  in octeon_cf_set_dmamode()
230 	timing = ata_timing_find_mode(dev->dma_mode);  in octeon_cf_set_dmamode()
231 	T0	= timing->cycle;  in octeon_cf_set_dmamode()
232 	Td	= timing->active;  in octeon_cf_set_dmamode()
233 	Tkr	= timing->recover;  in octeon_cf_set_dmamode()
234 	dma_ackh = timing->dmack_hold;  in octeon_cf_set_dmamode()
237 	/* dma_tim.s.tim_mult = 0 --> 4x */  in octeon_cf_set_dmamode()
242 	pause = 25 - dma_arq * 1000 /  in octeon_cf_set_dmamode()
247 	oe_n = max(T0 - oe_a, Tkr);  in octeon_cf_set_dmamode()
252 	c = (cf_port->dma_base & 8) >> 3;  in octeon_cf_set_dmamode()
282 	cvmx_write_csr(cf_port->dma_base + DMA_TIM, dma_tim.u64);  in octeon_cf_set_dmamode()
298 	struct ata_port *ap		= qc->dev->link->ap;  in octeon_cf_data_xfer8()
299 	void __iomem *data_addr		= ap->ioaddr.data_addr;  in octeon_cf_data_xfer8()
306 		while (words--) {  in octeon_cf_data_xfer8()
310 			 * Every 16 writes do a read so the bootbus  in octeon_cf_data_xfer8()
313 			if (--count == 0) {  in octeon_cf_data_xfer8()
314 				ioread8(ap->ioaddr.altstatus_addr);  in octeon_cf_data_xfer8()
325  * Handle a 16 bit I/O request.
337 	struct ata_port *ap		= qc->dev->link->ap;  in octeon_cf_data_xfer16()
338 	void __iomem *data_addr		= ap->ioaddr.data_addr;  in octeon_cf_data_xfer16()
345 		while (words--) {  in octeon_cf_data_xfer16()
349 			 * Every 16 writes do a read so the bootbus  in octeon_cf_data_xfer16()
352 			if (--count == 0) {  in octeon_cf_data_xfer16()
353 				ioread8(ap->ioaddr.altstatus_addr);  in octeon_cf_data_xfer16()
358 		while (words--) {  in octeon_cf_data_xfer16()
380  * Read the taskfile for 16bit non-True IDE only.
382 static void octeon_cf_tf_read16(struct ata_port *ap, struct ata_taskfile *tf)  in octeon_cf_tf_read16()  argument
386 	void __iomem *base = ap->ioaddr.data_addr;  in octeon_cf_tf_read16()
389 	tf->feature = blob >> 8;  in octeon_cf_tf_read16()
392 	tf->nsect = blob & 0xff;  in octeon_cf_tf_read16()
393 	tf->lbal = blob >> 8;  in octeon_cf_tf_read16()
396 	tf->lbam = blob & 0xff;  in octeon_cf_tf_read16()
397 	tf->lbah = blob >> 8;  in octeon_cf_tf_read16()
400 	tf->device = blob & 0xff;  in octeon_cf_tf_read16()
401 	tf->command = blob >> 8;  in octeon_cf_tf_read16()
403 	if (tf->flags & ATA_TFLAG_LBA48) {  in octeon_cf_tf_read16()
404 		if (likely(ap->ioaddr.ctl_addr)) {  in octeon_cf_tf_read16()
405 			iowrite8(tf->ctl | ATA_HOB, ap->ioaddr.ctl_addr);  in octeon_cf_tf_read16()
408 			tf->hob_feature = blob >> 8;  in octeon_cf_tf_read16()
411 			tf->hob_nsect = blob & 0xff;  in octeon_cf_tf_read16()
412 			tf->hob_lbal = blob >> 8;  in octeon_cf_tf_read16()
415 			tf->hob_lbam = blob & 0xff;  in octeon_cf_tf_read16()
416 			tf->hob_lbah = blob >> 8;  in octeon_cf_tf_read16()
418 			iowrite8(tf->ctl, ap->ioaddr.ctl_addr);  in octeon_cf_tf_read16()
419 			ap->last_ctl = tf->ctl;  in octeon_cf_tf_read16()
429 	void __iomem *base = ap->ioaddr.data_addr;  in octeon_cf_check_status16()
438 	struct ata_port *ap = link->ap;  in octeon_cf_softreset16()
439 	void __iomem *base = ap->ioaddr.data_addr;  in octeon_cf_softreset16()
444 	__raw_writew(ap->ctl, base + 0xe);  in octeon_cf_softreset16()
446 	__raw_writew(ap->ctl | ATA_SRST, base + 0xe);  in octeon_cf_softreset16()
448 	__raw_writew(ap->ctl, base + 0xe);  in octeon_cf_softreset16()
457 	classes[0] = ata_sff_dev_classify(&link->device[0], 1, &err);  in octeon_cf_softreset16()
463  * Load the taskfile for 16bit non-True IDE only.  The device_addr is
467 				const struct ata_taskfile *tf)  in octeon_cf_tf_load16()  argument
469 	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;  in octeon_cf_tf_load16()
471 	void __iomem *base = ap->ioaddr.data_addr;  in octeon_cf_tf_load16()
473 	if (tf->ctl != ap->last_ctl) {  in octeon_cf_tf_load16()
474 		iowrite8(tf->ctl, ap->ioaddr.ctl_addr);  in octeon_cf_tf_load16()
475 		ap->last_ctl = tf->ctl;  in octeon_cf_tf_load16()
478 	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {  in octeon_cf_tf_load16()
479 		__raw_writew(tf->hob_feature << 8, base + 0xc);  in octeon_cf_tf_load16()
480 		__raw_writew(tf->hob_nsect | tf->hob_lbal << 8, base + 2);  in octeon_cf_tf_load16()
481 		__raw_writew(tf->hob_lbam | tf->hob_lbah << 8, base + 4);  in octeon_cf_tf_load16()
483 			tf->hob_feature,  in octeon_cf_tf_load16()
484 			tf->hob_nsect,  in octeon_cf_tf_load16()
485 			tf->hob_lbal,  in octeon_cf_tf_load16()
486 			tf->hob_lbam,  in octeon_cf_tf_load16()
487 			tf->hob_lbah);  in octeon_cf_tf_load16()
490 		__raw_writew(tf->feature << 8, base + 0xc);  in octeon_cf_tf_load16()
491 		__raw_writew(tf->nsect | tf->lbal << 8, base + 2);  in octeon_cf_tf_load16()
492 		__raw_writew(tf->lbam | tf->lbah << 8, base + 4);  in octeon_cf_tf_load16()
494 			tf->feature,  in octeon_cf_tf_load16()
495 			tf->nsect,  in octeon_cf_tf_load16()
496 			tf->lbal,  in octeon_cf_tf_load16()
497 			tf->lbam,  in octeon_cf_tf_load16()
498 			tf->lbah);  in octeon_cf_tf_load16()
512  * as it must be written in a combined write with the command.
515 				const struct ata_taskfile *tf)  in octeon_cf_exec_command16()  argument
518 	void __iomem *base = ap->ioaddr.data_addr;  in octeon_cf_exec_command16()
521 	if (tf->flags & ATA_TFLAG_DEVICE) {  in octeon_cf_exec_command16()
522 		VPRINTK("device 0x%X\n", tf->device);  in octeon_cf_exec_command16()
523 		blob = tf->device;  in octeon_cf_exec_command16()
528 	DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);  in octeon_cf_exec_command16()
529 	blob |= (tf->command << 8);  in octeon_cf_exec_command16()
542 	struct ata_port *ap = qc->ap;  in octeon_cf_dma_setup()
545 	cf_port = ap->private_data;  in octeon_cf_dma_setup()
548 	qc->cursg = qc->sg;  in octeon_cf_dma_setup()
549 	cf_port->dma_finished = 0;  in octeon_cf_dma_setup()
550 	ap->ops->sff_exec_command(ap, &qc->tf);  in octeon_cf_dma_setup()
555  * Start a DMA transfer that was already setup
561 	struct octeon_cf_port *cf_port = qc->ap->private_data;  in octeon_cf_dma_start()
566 	VPRINTK("%d scatterlists\n", qc->n_elem);  in octeon_cf_dma_start()
569 	sg = qc->cursg;  in octeon_cf_dma_start()
577 	cvmx_write_csr(cf_port->dma_base + DMA_INT, mio_boot_dma_int.u64);  in octeon_cf_dma_start()
580 	cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, mio_boot_dma_int.u64);  in octeon_cf_dma_start()
588 	mio_boot_dma_cfg.s.rw = ((qc->tf.flags & ATA_TFLAG_WRITE) != 0);  in octeon_cf_dma_start()
592 	 * compact flashes deassert DMARQ for a short time between  in octeon_cf_dma_start()
595 	 * due to an error condition, a later timeout will force us to  in octeon_cf_dma_start()
601 	mio_boot_dma_cfg.s.size = sg_dma_len(sg) / 2 - 1;  in octeon_cf_dma_start()
609 		(mio_boot_dma_cfg.s.rw) ? "write" : "read", sg->length,  in octeon_cf_dma_start()
612 	cvmx_write_csr(cf_port->dma_base + DMA_CFG, mio_boot_dma_cfg.u64);  in octeon_cf_dma_start()
624 	struct ata_eh_info *ehi = &ap->link.eh_info;  in octeon_cf_dma_finished()
625 	struct octeon_cf_port *cf_port = ap->private_data;  in octeon_cf_dma_finished()
631 		ap->print_id, qc->tf.protocol, ap->hsm_task_state);  in octeon_cf_dma_finished()
634 	if (ap->hsm_task_state != HSM_ST_LAST)  in octeon_cf_dma_finished()
637 	dma_cfg.u64 = cvmx_read_csr(cf_port->dma_base + DMA_CFG);  in octeon_cf_dma_finished()
640 		qc->err_mask |= AC_ERR_HOST_BUS;  in octeon_cf_dma_finished()
641 		ap->hsm_task_state = HSM_ST_ERR;  in octeon_cf_dma_finished()
646 	dma_cfg.s.size = -1;  in octeon_cf_dma_finished()
647 	cvmx_write_csr(cf_port->dma_base + DMA_CFG, dma_cfg.u64);  in octeon_cf_dma_finished()
651 	cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, dma_int.u64);  in octeon_cf_dma_finished()
655 	cvmx_write_csr(cf_port->dma_base + DMA_INT, dma_int.u64);  in octeon_cf_dma_finished()
657 	status = ap->ops->sff_check_status(ap);  in octeon_cf_dma_finished()
661 	if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA))  in octeon_cf_dma_finished()
679 	spin_lock_irqsave(&host->lock, flags);  in octeon_cf_interrupt()
682 	for (i = 0; i < host->n_ports; i++) {  in octeon_cf_interrupt()
689 		ap = host->ports[i];  in octeon_cf_interrupt()
690 		cf_port = ap->private_data;  in octeon_cf_interrupt()
692 		dma_int.u64 = cvmx_read_csr(cf_port->dma_base + DMA_INT);  in octeon_cf_interrupt()
693 		dma_cfg.u64 = cvmx_read_csr(cf_port->dma_base + DMA_CFG);  in octeon_cf_interrupt()
695 		qc = ata_qc_from_tag(ap, ap->link.active_tag);  in octeon_cf_interrupt()
697 		if (!qc || (qc->tf.flags & ATA_TFLAG_POLLING))  in octeon_cf_interrupt()
701 			if (!sg_is_last(qc->cursg)) {  in octeon_cf_interrupt()
702 				qc->cursg = sg_next(qc->cursg);  in octeon_cf_interrupt()
707 				cf_port->dma_finished = 1;  in octeon_cf_interrupt()
710 		if (!cf_port->dma_finished)  in octeon_cf_interrupt()
712 		status = ioread8(ap->ioaddr.altstatus_addr);  in octeon_cf_interrupt()
717 			 * take a little while for the card to be  in octeon_cf_interrupt()
723 			cvmx_write_csr(cf_port->dma_base + DMA_INT,  in octeon_cf_interrupt()
725 			hrtimer_start_range_ns(&cf_port->delayed_finish,  in octeon_cf_interrupt()
734 	spin_unlock_irqrestore(&host->lock, flags);  in octeon_cf_interrupt()
744 	struct ata_port *ap = cf_port->ap;  in octeon_cf_delayed_finish()
745 	struct ata_host *host = ap->host;  in octeon_cf_delayed_finish()
751 	spin_lock_irqsave(&host->lock, flags);  in octeon_cf_delayed_finish()
756 	 * protected by host->lock.  in octeon_cf_delayed_finish()
758 	if (ap->hsm_task_state != HSM_ST_LAST || !cf_port->dma_finished)  in octeon_cf_delayed_finish()
761 	status = ioread8(ap->ioaddr.altstatus_addr);  in octeon_cf_delayed_finish()
769 	qc = ata_qc_from_tag(ap, ap->link.active_tag);  in octeon_cf_delayed_finish()
770 	if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))  in octeon_cf_delayed_finish()
773 	spin_unlock_irqrestore(&host->lock, flags);  in octeon_cf_delayed_finish()
780 	 * A maximum of 2^20 - 1 16 bit transfers are possible with  in octeon_cf_dev_config()
782 	 * (2^12 - 1 == 4095) to assure that this can never happen.  in octeon_cf_dev_config()
784 	dev->max_sectors = min(dev->max_sectors, 4095U);  in octeon_cf_dev_config()
797 	struct ata_port *ap = qc->ap;  in octeon_cf_qc_issue()
799 	switch (qc->tf.protocol) {  in octeon_cf_qc_issue()
801 		WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING);  in octeon_cf_qc_issue()
803 		ap->ops->sff_tf_load(ap, &qc->tf);  /* load tf registers */  in octeon_cf_qc_issue()
806 		ap->hsm_task_state = HSM_ST_LAST;  in octeon_cf_qc_issue()
810 		dev_err(ap->dev, "Error, ATAPI not supported\n");  in octeon_cf_qc_issue()
851 	int rv = -ENOMEM;  in octeon_cf_probe()
854 	node = pdev->dev.of_node;  in octeon_cf_probe()
856 		return -EINVAL;  in octeon_cf_probe()
858 	cf_port = devm_kzalloc(&pdev->dev, sizeof(*cf_port), GFP_KERNEL);  in octeon_cf_probe()
860 		return -ENOMEM;  in octeon_cf_probe()
862 	cf_port->is_true_ide = of_property_read_bool(node, "cavium,true-ide");  in octeon_cf_probe()
864 	if (of_property_read_u32(node, "cavium,bus-width", &bus_width) == 0)  in octeon_cf_probe()
874 		return -EINVAL;  in octeon_cf_probe()
876 	cs_num = reg_prop->value;  in octeon_cf_probe()
877 	cf_port->cs0 = be32_to_cpup(cs_num);  in octeon_cf_probe()
879 	if (cf_port->is_true_ide) {  in octeon_cf_probe()
882 					    "cavium,dma-engine-handle", 0);  in octeon_cf_probe()
892 					return -EINVAL;  in octeon_cf_probe()
894 				cf_port->dma_base = (u64)devm_ioremap(&pdev->dev, res_dma->start,  in octeon_cf_probe()
896 				if (!cf_port->dma_base) {  in octeon_cf_probe()
898 					return -EINVAL;  in octeon_cf_probe()
910 			return -EINVAL;  in octeon_cf_probe()
912 		cs1 = devm_ioremap(&pdev->dev, res_cs1->start,  in octeon_cf_probe()
918 			return -EINVAL;  in octeon_cf_probe()
921 		cf_port->cs1 = be32_to_cpup(cs_num);  in octeon_cf_probe()
926 		return -EINVAL;  in octeon_cf_probe()
928 	cs0 = devm_ioremap(&pdev->dev, res_cs0->start,  in octeon_cf_probe()
934 	host = ata_host_alloc(&pdev->dev, 1);  in octeon_cf_probe()
938 	ap = host->ports[0];  in octeon_cf_probe()
939 	ap->private_data = cf_port;  in octeon_cf_probe()
940 	pdev->dev.platform_data = cf_port;  in octeon_cf_probe()
941 	cf_port->ap = ap;  in octeon_cf_probe()
942 	ap->ops = &octeon_cf_ops;  in octeon_cf_probe()
943 	ap->pio_mask = ATA_PIO6;  in octeon_cf_probe()
944 	ap->flags |= ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING;  in octeon_cf_probe()
948 		ap->ioaddr.cmd_addr	= base;  in octeon_cf_probe()
949 		ata_sff_std_ports(&ap->ioaddr);  in octeon_cf_probe()
951 		ap->ioaddr.altstatus_addr = base + 0xe;  in octeon_cf_probe()
952 		ap->ioaddr.ctl_addr	= base + 0xe;  in octeon_cf_probe()
954 	} else if (cf_port->is_true_ide) {  in octeon_cf_probe()
956 		ap->ioaddr.cmd_addr	= base + (ATA_REG_CMD << 1) + 1;  in octeon_cf_probe()
957 		ap->ioaddr.data_addr	= base + (ATA_REG_DATA << 1);  in octeon_cf_probe()
958 		ap->ioaddr.error_addr	= base + (ATA_REG_ERR << 1) + 1;  in octeon_cf_probe()
959 		ap->ioaddr.feature_addr	= base + (ATA_REG_FEATURE << 1) + 1;  in octeon_cf_probe()
960 		ap->ioaddr.nsect_addr	= base + (ATA_REG_NSECT << 1) + 1;  in octeon_cf_probe()
961 		ap->ioaddr.lbal_addr	= base + (ATA_REG_LBAL << 1) + 1;  in octeon_cf_probe()
962 		ap->ioaddr.lbam_addr	= base + (ATA_REG_LBAM << 1) + 1;  in octeon_cf_probe()
963 		ap->ioaddr.lbah_addr	= base + (ATA_REG_LBAH << 1) + 1;  in octeon_cf_probe()
964 		ap->ioaddr.device_addr	= base + (ATA_REG_DEVICE << 1) + 1;  in octeon_cf_probe()
965 		ap->ioaddr.status_addr	= base + (ATA_REG_STATUS << 1) + 1;  in octeon_cf_probe()
966 		ap->ioaddr.command_addr	= base + (ATA_REG_CMD << 1) + 1;  in octeon_cf_probe()
967 		ap->ioaddr.altstatus_addr = cs1 + (6 << 1) + 1;  in octeon_cf_probe()
968 		ap->ioaddr.ctl_addr	= cs1 + (6 << 1) + 1;  in octeon_cf_probe()
971 		ap->mwdma_mask	= enable_dma ? ATA_MWDMA4 : 0;  in octeon_cf_probe()
973 		/* True IDE mode needs a timer to poll for not-busy.  */  in octeon_cf_probe()
974 		hrtimer_init(&cf_port->delayed_finish, CLOCK_MONOTONIC,  in octeon_cf_probe()
976 		cf_port->delayed_finish.function = octeon_cf_delayed_finish;  in octeon_cf_probe()
987 		ap->ioaddr.data_addr	= base + ATA_REG_DATA;  in octeon_cf_probe()
988 		ap->ioaddr.nsect_addr	= base + ATA_REG_NSECT;  in octeon_cf_probe()
989 		ap->ioaddr.lbal_addr	= base + ATA_REG_LBAL;  in octeon_cf_probe()
990 		ap->ioaddr.ctl_addr	= base + 0xe;  in octeon_cf_probe()
991 		ap->ioaddr.altstatus_addr = base + 0xe;  in octeon_cf_probe()
993 	cf_port->c0 = ap->ioaddr.ctl_addr;  in octeon_cf_probe()
995 	rv = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));  in octeon_cf_probe()
999 	ata_port_desc(ap, "cmd %p ctl %p", base, ap->ioaddr.ctl_addr);  in octeon_cf_probe()
1001 	dev_info(&pdev->dev, "version " DRV_VERSION" %d bit%s.\n",  in octeon_cf_probe()
1003 		 cf_port->is_true_ide ? ", True IDE" : "");  in octeon_cf_probe()
1016 	if (cf_port->dma_base) {  in octeon_cf_shutdown()
1019 		dma_cfg.s.size = -1;  in octeon_cf_shutdown()
1020 		cvmx_write_csr(cf_port->dma_base + DMA_CFG, dma_cfg.u64);  in octeon_cf_shutdown()
1024 		cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, dma_int.u64);  in octeon_cf_shutdown()
1028 		cvmx_write_csr(cf_port->dma_base + DMA_INT, dma_int.u64);  in octeon_cf_shutdown()
1030 		__raw_writeb(0, cf_port->c0);  in octeon_cf_shutdown()
1032 		__raw_writeb(ATA_SRST, cf_port->c0);  in octeon_cf_shutdown()
1034 		__raw_writeb(0, cf_port->c0);  in octeon_cf_shutdown()
1041 		.compatible = "cavium,ebt3000-compact-flash",
1063 MODULE_DESCRIPTION("low-level driver for Cavium OCTEON Compact Flash PATA");