668  *	hpt37x_calibrate_dpll		-	Calibrate the DPLL loop
671  *	Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this
692 			/* Turn off tuning, we have the DPLL set */  in hpt37x_calibrate_dpll()
977 		 *	use a 50MHz DPLL by choice  in hpt37x_init_one()
980 		int dpll, adjust;  in hpt37x_init_one()  local
982 		/* Compute DPLL */  in hpt37x_init_one()
983 		dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2;  in hpt37x_init_one()
985 		f_low = (MHz[clock_slot] * 48) / MHz[dpll];  in hpt37x_init_one()
990 		/* Select the DPLL clock. */  in hpt37x_init_one()
1010 			pr_err("DPLL did not stabilize!\n");  in hpt37x_init_one()
1013 		if (dpll == 3)  in hpt37x_init_one()
1018 		pr_info("bus clock %dMHz, using %dMHz DPLL\n",  in hpt37x_init_one()
1019 			MHz[clock_slot], MHz[dpll]);  in hpt37x_init_one()
1024 		 *	DPLL on the HPT372 which means we don't have to worry  in hpt37x_init_one()