26  * called (PCC) Platform Communication Channel. This is a generic mailbox like
28  * See drivers/mailbox/pcc.c for details on PCC.
30  * Finer details about the PCC and CPPC spec are available in the ACPI v5.1 and
52 	bool pending_pcc_write_cmd;	/* Any pending/batched PCC write cmds? */
53 	bool platform_owns_pcc;		/* Ownership of PCC subspace */
54 	unsigned int pcc_write_cnt;	/* Running count of PCC write commands */
57 	 * Lock to provide controlled access to the PCC channel.
61 	 * before reading or writing to PCC subspace
80 /* Array to represent the PCC channel per subspace ID */
88  * include the type of register (e.g. PCC, System IO, FFH etc.)
94 /* pcc mapped address + header size + offset within PCC subspace */
98 /* Check if a CPC register is in PCC */
116  * to PCC commands. Keeping it high enough to cover emulators where
207 	 * Poll PCC status register every 3us(delay_us) for maximum of  in check_pcc_chan()
208 	 * deadline_us(timeout_us) until PCC command complete bit is set(cond)  in check_pcc_chan()
221 		pr_err("PCC check channel failed for ss: %d. ret=%d\n",  in check_pcc_chan()
228  * This function transfers the ownership of the PCC to the platform
241 	 * the channel before writing to PCC space  in send_pcc_cmd()
286 				pr_debug("PCC cmd for subspace %d not sent due to MPAR limit",  in send_pcc_cmd()
308 		pr_err("Err sending PCC mbox message. ss: %d cmd:%d, ret:%d\n",  in send_pcc_cmd()
313 	/* wait for completion and check for PCC errro bit */  in send_pcc_cmd()
532 			pr_err("Failed to find PCC channel for subspace %d\n",  in register_pcc_channel()
538 		 * The PCC mailbox controller driver should  in register_pcc_channel()
540 		 * PCC channels) and stored pointers to the  in register_pcc_channel()
546 			pr_err("No PCC subspace found for %d CPPC\n",  in register_pcc_channel()
565 			pr_err("Failed to ioremap PCC comm region mem for %d\n",  in register_pcc_channel()
591  * pcc_data_alloc() - Allocate the pcc_data memory for pcc subspace
654  *			ResourceTemplate(){Register(PCC, 32, 0, 0x120, 2)},
656  *			ResourceTemplate(){Register(PCC, 32, 0, 0x124, 2)},
658  *			ResourceTemplate(){Register(PCC, 32, 0, 0x128, 2)},
660  *			ResourceTemplate(){Register(PCC, 32, 0, 0x12C, 2)},
662  *			ResourceTemplate(){Register(PCC, 32, 0, 0x130, 2)},
664  *			ResourceTemplate(){Register(PCC, 32, 0, 0x110, 2)},
673  * e.g. a sample PCC entry has the following encoding:
676  *		PCC,
763 			 * The PCC Subspace index is encoded inside  in acpi_cppc_processor_probe()
764 			 * the CPC table entries. The same PCC index  in acpi_cppc_processor_probe()
765 			 * will be used for all the PCC entries,  in acpi_cppc_processor_probe()
774 					pr_debug("Mismatched PCC ids.\n");  in acpi_cppc_processor_probe()
788 					/* Support only PCC ,SYS MEM and FFH type regs */  in acpi_cppc_processor_probe()
822 	/* Register PCC channel once for all PCC subspace ID. */  in acpi_cppc_processor_probe()
944  * as fast as possible. We have already mapped the PCC subspace during init, so
985 			pr_debug("Error: Cannot read %u bit width from PCC for ss: %d\n",  in cpc_read()
1024 			pr_debug("Error: Cannot write %u bit width to PCC for ss: %d\n",  in cpc_write()
1106 	/* Are any of the regs PCC ?*/  in cppc_get_perf_caps()
1117 		/* Ring doorbell once to update PCC subspace */  in cppc_get_perf_caps()
1199 	/* Are any of the regs PCC ?*/  in cppc_get_perf_ctrs()
1209 		/* Ring doorbell once to update PCC subspace */  in cppc_get_perf_ctrs()
1289 		 * Update the pending_write to make sure a PCC CMD_READ will not  in cppc_set_perf()
1306 	 * This is Phase-II where we transfer the ownership of PCC to Platform  in cppc_set_perf()
1321 	 * PCC ownership to the platform, then one of the following will be TRUE  in cppc_set_perf()
1329 	 *     3. Some other CPU executing pcc CMD_READ has stolen the  in cppc_set_perf()
1341 	 * doorbell and transferred the ownership of PCC to platform. So this  in cppc_set_perf()
1343 	 * triggering the doorbell it makes sure that the PCC channel ownership  in cppc_set_perf()
1346 	 * there was a pcc CMD_READ waiting on down_write and it steals the lock  in cppc_set_perf()
1347 	 * before the pcc CMD_WRITE is completed. pcc_send_cmd checks for this  in cppc_set_perf()
1375  * on the number and frequency of PCC commands the platform can handle.