Lines Matching +full:mode +full:- +full:xxx
10 * Copyright (C) 2001 - 2005 Tensilica, Inc.
21 #include <asm/asm-offsets.h>
27 /* First-level exception handler for unaligned exceptions.
33 /* Big and little endian 16-bit values are located in
35 * abstract the notion of extracting a 16-bit value from a
98 * -------------------
103 * -----------------------------
107 * XXX 0011 ssss tttt 0010
108 * XXX 0100 ssss tttt 0010
111 * XXX 0111 ssss tttt 0010
112 * XXX 1000 ssss tttt 0010
114 * XXX 1010 0010
116 * XXX 1100 0010
117 * XXX 1101 0010
118 * XXX 1110 0010
120 * -----------------------------
122 * sub-opcode (NIBBLE_R) -+ | |
123 * t field (NIBBLE_T) -----------+ |
124 * major opcode (NIBBLE_OP0) --------------+
192 * mappings. However, high-level interrupt handlers might
217 addi a6, a5, -OP0_S32I_N
238 l32e a5, a3, -8
239 l32e a6, a3, -4
247 addi a7, a7, 2 # increment PC (assume 16-bit insn)
262 addi a5, a5, -OP1_L16SI
336 bbsi.l a0, PS_UM_BIT, 2f # jump if user mode
349 addi a7, a7, 2 # incr. PC,assume 16-bit instruction
352 addi a5, a5, -OP0_S32I_N
355 addi a7, a7, 1 # increment PC, 32-bit instruction
357 addi a7, a7, 3 # increment PC, 32-bit instruction
364 movi a5, -1
365 __extl a3, a3 # get 16-bit value
366 __exth a6, a5 # get 16-bit mask ffffffff:ffff0000
376 movi a5, -1 # mask: ffffffff:XXXX0000
382 __src_b a8, a5, a6 # lo-mask F..F0..0 (BE) 0..0F..F (LE)
383 __src_b a6, a6, a5 # hi-mask 0..0F..F (BE) F..F0..0 (LE)
385 l32e a5, a4, -8
393 s32e a5, a4, -8
394 l32e a8, a4, -4
403 s32e a6, a4, -4
414 addi a4, a4, -1 # decrement LCOUNT and set
421 /* Update icount if we're single-stepping in userspace. */
469 bbsi.l a0, PS_UM_BIT, 1f # jump if user mode