Lines Matching +full:0 +full:x8000000a
72 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
74 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
75 #define TSC_RATIO_MIN 0x0000000000000001ULL
76 #define TSC_RATIO_MAX 0x000000ffffffffffULL
89 #define TSC_RATIO_DEFAULT 0x0100000000ULL
193 static bool __read_mostly dump_invalid_vmcb = 0;
213 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
224 for (i = 0; i < NUM_MSR_MAPS; i++) { in svm_msrpm_offset()
254 asm volatile (__ex("invlpga %1, %0") : : "c"(asid), "a"(addr)); in invlpga()
305 return 0; in svm_set_efer()
317 u32 ret = 0; in svm_get_interrupt_shadow()
328 if (mask == 0) in svm_set_interrupt_shadow()
339 if (nrips && svm->vmcb->control.next_rip != 0) { in skip_emulated_instruction()
346 return 0; in skip_emulated_instruction()
350 svm_set_interrupt_shadow(vcpu, 0); in skip_emulated_instruction()
382 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) in svm_queue_exception()
422 * all osvw.status bits inside that length, including bit 0 (which is in svm_init_osvw()
424 * osvw_len is 0 then osvw_status[0] carries no information. We need to in svm_init_osvw()
428 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10) in svm_init_osvw()
438 return 0; in has_svm()
505 uint64_t len, status = 0; in svm_hardware_enable()
514 osvw_status = osvw_len = 0; in svm_hardware_enable()
522 osvw_status = osvw_len = 0; in svm_hardware_enable()
528 return 0; in svm_hardware_enable()
566 return 0; in svm_cpu_init()
580 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) in direct_access_msr_slot()
624 bit_write = 2 * (msr & 0x0f) + 1; in msr_write_intercepted()
647 read = 0; in set_msr_interception_bitmap()
650 write = 0; in set_msr_interception_bitmap()
653 bit_read = 2 * (msr & 0x0f); in set_msr_interception_bitmap()
654 bit_write = 2 * (msr & 0x0f) + 1; in set_msr_interception_bitmap()
681 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); in svm_vcpu_alloc_msrpm()
690 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { in svm_vcpu_init_msrpm()
713 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { in svm_msr_filter_changed()
726 for (i = 0; i < MSRPM_OFFSETS; ++i) { in add_msr_offset()
753 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets)); in init_msrpm_offsets()
755 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { in init_msrpm_offsets()
781 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0); in svm_disable_lbrv()
782 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0); in svm_disable_lbrv()
783 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 0, 0); in svm_disable_lbrv()
784 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 0, 0); in svm_disable_lbrv()
848 if (cpuid_eax(0x80000000) < 0x8000001f) in svm_adjust_mmio_mask()
856 enc_bit = cpuid_ebx(0x8000001f) & 0x3f; in svm_adjust_mmio_mask()
872 mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0; in svm_adjust_mmio_mask()
888 iopm_base = 0; in svm_hardware_teardown()
895 supported_xss = 0; in svm_set_cpu_caps()
897 /* CPUID 0x80000001 and 0x8000000A (SVM features) */ in svm_set_cpu_caps()
908 /* CPUID 0x80000008 */ in svm_set_cpu_caps()
930 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); in svm_hardware_setup()
951 pause_filter_count = 0; in svm_hardware_setup()
952 pause_filter_thresh = 0; in svm_hardware_setup()
954 pause_filter_thresh = 0; in svm_hardware_setup()
1041 return 0; in svm_hardware_setup()
1050 seg->selector = 0; in init_seg()
1053 seg->limit = 0xffff; in init_seg()
1054 seg->base = 0; in init_seg()
1059 seg->selector = 0; in init_sys_seg()
1061 seg->limit = 0xffff; in init_sys_seg()
1062 seg->base = 0; in init_sys_seg()
1068 u64 g_tsc_offset = 0; in svm_write_l1_tsc_offset()
1107 svm->vcpu.arch.hflags = 0; in init_vmcb()
1177 save->cs.selector = 0xf000; in init_vmcb()
1178 save->cs.base = 0xffff0000; in init_vmcb()
1182 save->cs.limit = 0xffff; in init_vmcb()
1184 save->gdtr.limit = 0xffff; in init_vmcb()
1185 save->idtr.limit = 0xffff; in init_vmcb()
1190 svm_set_efer(&svm->vcpu, 0); in init_vmcb()
1191 save->dr6 = 0xffff0ff0; in init_vmcb()
1193 save->rip = 0x0000fff0; in init_vmcb()
1214 save->cr3 = 0; in init_vmcb()
1215 save->cr4 = 0; in init_vmcb()
1217 svm->asid_generation = 0; in init_vmcb()
1219 svm->nested.vmcb12_gpa = 0; in init_vmcb()
1220 svm->vcpu.arch.hflags = 0; in init_vmcb()
1269 svm->spec_ctrl = 0; in svm_vcpu_reset()
1270 svm->virt_spec_ctrl = 0; in svm_vcpu_reset()
1293 BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0); in svm_create_vcpu()
1321 svm->asid_generation = 0; in svm_create_vcpu()
1325 vcpu->arch.microcode_version = 0x01000065; in svm_create_vcpu()
1327 return 0; in svm_create_vcpu()
1367 svm->asid_generation = 0; in svm_vcpu_load()
1378 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) in svm_vcpu_load()
1417 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) in svm_vcpu_put()
1474 control->int_vector = 0x0; in svm_set_vintr()
1477 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); in svm_set_vintr()
1548 var->g = s->limit > 0xfffff; in svm_get_segment()
1562 var->type |= 0x2; in svm_get_segment()
1576 var->type |= 0x1; in svm_get_segment()
1586 var->db = 0; in svm_get_segment()
1704 return 0; in svm_set_cr4()
1778 get_debugreg(vcpu->arch.db[0], 0); in svm_sync_dirty_debug_regs()
1850 return 0; in db_interception()
1863 return 0; in bp_interception()
1873 kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0); in ac_interception()
1910 if (value != 0xb600000000010015ULL) in is_erratum_383()
1914 for (i = 0; i < 6; ++i) in is_erratum_383()
1915 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0); in is_erratum_383()
1991 return 0; in shutdown_interception()
2002 string = (io_info & SVM_IOIO_STR_MASK) != 0; in io_interception()
2003 in = (io_info & SVM_IOIO_TYPE_MASK) != 0; in io_interception()
2005 return kvm_emulate_instruction(vcpu, 0); in io_interception()
2052 kvm_inject_gp(&svm->vcpu, 0); in vmload_interception()
2078 kvm_inject_gp(&svm->vcpu, 0); in vmsave_interception()
2187 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) { in xsetbv_interception()
2212 u32 error_code = 0; in task_switch_interception()
2254 return 0; in task_switch_interception()
2288 return kvm_emulate_instruction(&svm->vcpu, 0); in invlpg_interception()
2296 return kvm_emulate_instruction(&svm->vcpu, 0); in emulate_on_interception()
2347 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0)) in cr_interception()
2356 err = 0; in cr_interception()
2362 case 0: in cr_interception()
2385 case 0: in cr_interception()
2416 if (svm->vcpu.guest_debug == 0) { in dr_interception()
2461 return 0; in cr8_write_interception()
2466 msr->data = 0; in svm_get_msr_feature()
2474 return 0; in svm_get_msr_feature()
2479 return 0; in svm_get_msr_feature()
2520 * safely return them on rdmsr. They will always be 0 until LBRV is in svm_get_msr()
2568 if (family < 0 || model < 0) in svm_get_msr()
2571 msr_info->data = 0; in svm_get_msr()
2573 if (family == 0x15 && in svm_get_msr()
2574 (model >= 0x2 && model < 0x20)) in svm_get_msr()
2575 msr_info->data = 0x1E; in svm_get_msr()
2584 return 0; in svm_get_msr()
2614 return 0; in svm_set_vm_cr()
2672 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_PRED_CMD, 0, 1); in svm_set_msr()
2726 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n", in svm_set_msr()
2735 if (data & (1ULL<<0)) in svm_set_msr()
2746 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data); in svm_set_msr()
2773 return 0; in svm_set_msr()
2808 bool in_kernel = (svm_get_cpl(vcpu) == 0); in pause_interception()
2854 kvm_inject_gp(vcpu, 0); in invpcid_interception()
2942 pr_err("%-20s%04x\n", "cr_read:", control->intercepts[INTERCEPT_CR] & 0xffff); in dump_vmcb()
2944 pr_err("%-20s%04x\n", "dr_read:", control->intercepts[INTERCEPT_DR] & 0xffff); in dump_vmcb()
3060 *error_code = 0; in svm_get_exit_info()
3096 return 0; in handle_exit()
3103 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x " in handle_exit()
3104 "exit_code 0x%x\n", in handle_exit()
3113 vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%x\n", exit_code); in handle_exit()
3119 vcpu->run->internal.data[0] = exit_code; in handle_exit()
3121 return 0; in handle_exit()
3296 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes in enable_irq_window()
3340 return 0; in svm_set_tss_addr()
3345 return 0; in svm_set_identity_map_addr()
3410 svm->int3_injected = 0; in svm_complete_interrupts()
3474 control->event_inj = 0; in svm_cancel_injection()
3637 svm->next_rip = 0; in svm_vcpu_run()
3640 svm->nested.nested_run_pending = 0; in svm_vcpu_run()
3701 return 0; in is_disabled()
3710 hypercall[0] = 0x0f; in svm_patch_hypercall()
3711 hypercall[1] = 0x01; in svm_patch_hypercall()
3712 hypercall[2] = 0xd9; in svm_patch_hypercall()
3717 return 0; in svm_check_processor_compat()
3740 return 0; in svm_get_mt_mask()
3761 best = kvm_find_cpuid_entry(vcpu, 0x8000001F, 0); in svm_vcpu_after_set_cpuid()
3763 vcpu->arch.cr3_lm_rsvd_bits &= ~(1UL << (best->ebx & 0x3f)); in svm_vcpu_after_set_cpuid()
3896 cr0 &= 0xfUL; in svm_check_intercept()
3897 val &= 0xfUL; in svm_check_intercept()
3916 vmcb->control.exit_info_1 = 0; in svm_check_intercept()
3932 exit_info = ((info->src_val & 0xffff) << 16) | in svm_check_intercept()
3936 exit_info = (info->dst_val & 0xffff) << 16; in svm_check_intercept()
3988 vcpu->arch.mcg_cap &= 0x1ff; in svm_setup_mce()
4022 put_smstate(u64, smstate, 0x7ed8, 1); in svm_pre_enter_smm()
4024 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb12_gpa); in svm_pre_enter_smm()
4034 return 0; in svm_pre_enter_smm()
4041 int ret = 0; in svm_pre_leave_smm()
4044 u64 saved_efer = GET_SMSTATE(u64, smstate, 0x7ed0); in svm_pre_leave_smm()
4045 u64 guest = GET_SMSTATE(u64, smstate, 0x7ed8); in svm_pre_leave_smm()
4046 u64 vmcb12_gpa = GET_SMSTATE(u64, smstate, 0x7ee0); in svm_pre_leave_smm()
4096 * return 0 instead of the correct guest instruction bytes. in svm_can_emulate_instruction()
4099 * uses a special opcode which attempts to read data using CPL=0 in svm_can_emulate_instruction()
4105 * returned 0 in GuestIntrBytes field of the VMCB. in svm_can_emulate_instruction()
4110 * Otherwise, vCPU CR4.SMEP=0, errata could be triggered by any vCPU CPL. in svm_can_emulate_instruction()
4186 return 0; in svm_vm_init()