cpu/mtrr/mtrr.c

1 /*  Generic MTRR (Memory Type Range Register) driver.
3     Copyright (C) 1997-2000  Richard Gooch
29     on 6-7 March 2002.
31     System Programming Guide; Section 9.11. (1997 edition - PPro).
85 	if (ops->vendor && ops->vendor < X86_VENDOR_NUM)  in set_mtrr_ops()
86 		mtrr_ops[ops->vendor] = ops;  in set_mtrr_ops()
89 /*  Returns non-zero if we have the write-combining memory type  */
98 		 * write-combining. Don't allow it and leave room for other  in have_wrcomb()
101 		if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&  in have_wrcomb()
102 		    dev->device == PCI_DEVICE_ID_SERVERWORKS_LE &&  in have_wrcomb()
103 		    dev->revision <= 5) {  in have_wrcomb()
104 			pr_info("Serverworks LE rev < 6 detected. Write-combining disabled.\n");  in have_wrcomb()
110 		 * write combining memory may resulting in data corruption  in have_wrcomb()
112 		if (dev->vendor == PCI_VENDOR_ID_INTEL &&  in have_wrcomb()
113 		    dev->device == PCI_DEVICE_ID_INTEL_82451NX) {  in have_wrcomb()
114 			pr_info("Intel 450NX MMC detected. Write-combining disabled.\n");  in have_wrcomb()
120 	return mtrr_if->have_wrcomb ? mtrr_if->have_wrcomb() : 0;  in have_wrcomb()
155  * mtrr_rendezvous_handler - Work done in the synchronization handler. Executed
174 	 * all the cpu's we do mtrr_if->set_all() (On the logical cpu that  in mtrr_rendezvous_handler()
178 	if (data->smp_reg != ~0U) {  in mtrr_rendezvous_handler()
179 		mtrr_if->set(data->smp_reg, data->smp_base,  in mtrr_rendezvous_handler()
180 			     data->smp_size, data->smp_type);  in mtrr_rendezvous_handler()
182 		mtrr_if->set_all();  in mtrr_rendezvous_handler()
196  * set_mtrr - update mtrrs on all processors
207  * 4. Enter no-fill cache mode
223  * (the CPU vendors may each do it differently, so we call mtrr_if->set()
267  * mtrr_add_page - Add a memory type region
273  * Memory type region registers control the caching on newer Intel and
290  * %MTRR_TYPE_UNCACHABLE - No caching
292  * %MTRR_TYPE_WRBACK - Write data back in bursts whenever
294  * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts
296  * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes
309 		return -ENXIO;  in mtrr_add_page()
311 	error = mtrr_if->validate_add_page(base, size, type);  in mtrr_add_page()
317 		return -EINVAL;  in mtrr_add_page()
320 	/* If the type is WC, check that this processor supports it */  in mtrr_add_page()
322 		pr_warn("your processor doesn't support write-combining\n");  in mtrr_add_page()
323 		return -ENOSYS;  in mtrr_add_page()
328 		return -EINVAL;  in mtrr_add_page()
331 	if ((base | (base + size - 1)) >>  in mtrr_add_page()
332 	    (boot_cpu_data.x86_phys_bits - PAGE_SHIFT)) {  in mtrr_add_page()
334 		return -EINVAL;  in mtrr_add_page()
337 	error = -EINVAL;  in mtrr_add_page()
338 	replace = -1;  in mtrr_add_page()
340 	/* No CPU hotplug when we change MTRR entries */  in mtrr_add_page()
346 		mtrr_if->get(i, &lbase, &lsize, &ltype);  in mtrr_add_page()
347 		if (!lsize || base > lbase + lsize - 1 ||  in mtrr_add_page()
348 		    base + size - 1 < lbase)  in mtrr_add_page()
354 		if (base < lbase || base + size - 1 > lbase + lsize - 1) {  in mtrr_add_page()
356 			    base + size - 1 >= lbase + lsize - 1) {  in mtrr_add_page()
359 					replace = replace == -1 ? i : -2;  in mtrr_add_page()
383 	i = mtrr_if->get_free_region(base, size, replace);  in mtrr_add_page()
398 		pr_info("no more MTRRs available\n");  in mtrr_add_page()
409 	if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) {  in mtrr_check()
413 		return -1;  in mtrr_check()
419  * mtrr_add - Add a memory type region
425  * Memory type region registers control the caching on newer Intel and
442  * %MTRR_TYPE_UNCACHABLE - No caching
444  * %MTRR_TYPE_WRBACK - Write data back in bursts whenever
446  * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts
448  * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes
457 		return -ENODEV;  in mtrr_add()
459 		return -EINVAL;  in mtrr_add()
465  * mtrr_del_page - delete a memory type region
483 	int error = -EINVAL;  in mtrr_del_page()
486 		return -ENODEV;  in mtrr_del_page()
489 	/* No CPU hotplug when we change MTRR entries */  in mtrr_del_page()
495 			mtrr_if->get(i, &lbase, &lsize, &ltype);  in mtrr_del_page()
502 			pr_debug("no MTRR for %lx000,%lx000 found\n",  in mtrr_del_page()
511 	mtrr_if->get(reg, &lbase, &lsize, &ltype);  in mtrr_del_page()
520 	if (--mtrr_usage_table[reg] < 1)  in mtrr_del_page()
530  * mtrr_del - delete a memory type region
546 		return -ENODEV;  in mtrr_del()
548 		return -EINVAL;  in mtrr_del()
553  * arch_phys_wc_add - add a WC MTRR and handle errors if PAT is unavailable
558  * attempts to add a WC MTRR covering size bytes starting at base and
576 		pr_warn("Failed to add WC MTRR for [%p-%p]; performance may suffer.",  in arch_phys_wc_add()
577 			(void *)base, (void *)(base + size - 1));  in arch_phys_wc_add()
585  * arch_phys_wc_del - undoes arch_phys_wc_add
597 		mtrr_del(handle - MTRR_TO_PHYS_WC_OFFSET, 0, 0);  in arch_phys_wc_del()
603  * arch_phys_wc_index - translates arch_phys_wc_add's return value
609  * Note: There is no legitimate use for this function, except possibly
616 		return -1;  in arch_phys_wc_index()
618 		return handle - MTRR_TO_PHYS_WC_OFFSET;  in arch_phys_wc_index()
652 		mtrr_if->get(i, &mtrr_value[i].lbase,  in mtrr_save()
681 #define SIZE_OR_MASK_BITS(n)  (~((1ULL << ((n) - PAGE_SHIFT)) - 1))
683  * mtrr_bp_init - initialize mtrrs on the boot CPU
734 				/* Pre-Athlon (K6) AMD CPU MTRRs */  in mtrr_bp_init()
772 				mtrr_if->set_all();  in mtrr_bp_init()
816  * Save current fixed-range MTRR state of the first cpu in cpu_online_mask.
864 	mtrr_if->set_all();  in mtrr_bp_restore()
879 	 * The CPU has no MTRR and seems to not support SMP. They have  in mtrr_init_finialize()
884 	 * suspend/resume? If no, we should remove the code.  in mtrr_init_finialize()