cpu/mce/intel.c

1 // SPDX-License-Identifier: GPL-2.0
16 #include <asm/intel-family.h>
136 	 * Reset the counter if we've logged an error in the last poll  in mce_intel_cmci_poll()
176 unsigned long cmci_intel_adjust_timer(unsigned long interval)  in cmci_intel_adjust_timer()  argument
188 		 * We switch back to interrupt mode once the poll timer has  in cmci_intel_adjust_timer()
190 		 * interval is back to our poll interval.  in cmci_intel_adjust_timer()
211 		/* We have shiny weather. Let the poll do whatever it thinks. */  in cmci_intel_adjust_timer()
212 		return interval;  in cmci_intel_adjust_timer()
244 		pr_notice("CMCI storm detected: switching to poll mode\n");  in cmci_storm_detect()
312 		/* Did the enable bit stick? -- the bank supports CMCI */  in cmci_discover()
482 	switch (c->x86_model) {  in intel_ppin_init()
530 	if ((c->x86 == 6) &&  in intel_filter_mce()
531 	    ((c->x86_model == INTEL_FAM6_HASWELL) ||  in intel_filter_mce()
532 	     (c->x86_model == INTEL_FAM6_HASWELL_L) ||  in intel_filter_mce()
533 	     (c->x86_model == INTEL_FAM6_BROADWELL) ||  in intel_filter_mce()
534 	     (c->x86_model == INTEL_FAM6_HASWELL_G)) &&  in intel_filter_mce()
535 	    (m->bank == 0) &&  in intel_filter_mce()
536 	    ((m->status & 0xa0000000ffffffff) == 0x80000000000f0005))  in intel_filter_mce()