120 static enum smca_bank_types smca_get_bank_type(unsigned int bank)  in smca_get_bank_type()  argument
124 	if (bank >= MAX_NR_BANKS)  in smca_get_bank_type()
127 	b = &smca_banks[bank];  in smca_get_bank_type()
185  * So to define a unique name for each bank, we use a temp c-string to append
214 static void smca_set_misc_banks_map(unsigned int bank, unsigned int cpu)  in smca_set_misc_banks_map()  argument
222 	if (rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high))  in smca_set_misc_banks_map()
228 	if (rdmsr_safe(MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high))  in smca_set_misc_banks_map()
232 		per_cpu(smca_misc_banks_map, cpu) |= BIT(bank);  in smca_set_misc_banks_map()
236 static void smca_configure(unsigned int bank, unsigned int cpu)  in smca_configure()  argument
241 	u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank);  in smca_configure()
248 		 * bank. It also means that the OS will configure deferred  in smca_configure()
257 		 * SMCA sets the Deferred Error Interrupt type per bank.  in smca_configure()
273 	smca_set_misc_banks_map(bank, cpu);  in smca_configure()
275 	/* Return early if this bank was already initialized. */  in smca_configure()
276 	if (smca_banks[bank].hwid && smca_banks[bank].hwid->hwid_mcatype != 0)  in smca_configure()
279 	if (rdmsr_safe(MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) {  in smca_configure()
280 		pr_warn("Failed to read MCA_IPID for bank %d\n", bank);  in smca_configure()
290 			smca_banks[bank].hwid = s_hwid;  in smca_configure()
291 			smca_banks[bank].id = low;  in smca_configure()
292 			smca_banks[bank].sysfs_id = s_hwid->count++;  in smca_configure()
306 static inline bool is_shared_bank(int bank)  in is_shared_bank()  argument
310 	 * a shared bank.  in is_shared_bank()
315 	/* Bank 4 is for northbridge reporting and is thus shared */  in is_shared_bank()
316 	return (bank == 4);  in is_shared_bank()
339 static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits)  in lvt_interrupt_supported()  argument
342 	 * bank 4 supports APIC LVT interrupts implicitly since forever.  in lvt_interrupt_supported()
344 	if (bank == 4)  in lvt_interrupt_supported()
349 	 * bank can generate APIC LVT interrupts  in lvt_interrupt_supported()
360 		       "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu,  in lvt_off_valid()
361 		       b->bank, b->block, b->address, hi, lo);  in lvt_off_valid()
375 		       "for bank %d, block %d (MSR%08X=0x%x%08x)\n",  in lvt_off_valid()
376 		       b->cpu, apic, b->bank, b->block, b->address, hi, lo);  in lvt_off_valid()
383 /* Reprogram MCx_MISC MSR behind this threshold bank. */
489 static u32 smca_get_block_address(unsigned int bank, unsigned int block,  in smca_get_block_address()  argument
493 		return MSR_AMD64_SMCA_MCx_MISC(bank);  in smca_get_block_address()
495 	if (!(per_cpu(smca_misc_banks_map, cpu) & BIT(bank)))  in smca_get_block_address()
498 	return MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1);  in smca_get_block_address()
502 			     unsigned int bank, unsigned int block,  in get_block_address()  argument
507 	if ((bank >= per_cpu(mce_num_banks, cpu)) || (block >= NR_BLOCKS))  in get_block_address()
511 		return smca_get_block_address(bank, block, cpu);  in get_block_address()
516 		addr = msr_ops.misc(bank);  in get_block_address()
530 prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr,  in prepare_threshold_block()  argument
539 		per_cpu(bank_map, cpu) |= (1 << bank);  in prepare_threshold_block()
543 	b.bank			= bank;  in prepare_threshold_block()
546 	b.interrupt_capable	= lvt_interrupt_supported(bank, misc_high);  in prepare_threshold_block()
578 	enum smca_bank_types bank_type = smca_get_bank_type(m->bank);  in amd_filter_mce()
589 		if (m->bank == 4 && XEC(m->status, 0x1f) == 0x5)  in amd_filter_mce()
599  * - Prevent possible spurious interrupts from the IF bank on Family 0x17
602 static void disable_err_thresholding(struct cpuinfo_x86 *c, unsigned int bank)  in disable_err_thresholding()  argument
609 	if (c->x86 == 0x15 && bank == 4) {  in disable_err_thresholding()
616 		if (smca_get_bank_type(bank) != SMCA_IF)  in disable_err_thresholding()
619 		msrs[0] = MSR_AMD64_SMCA_MCx_MISC(bank);  in disable_err_thresholding()
644 	unsigned int bank, block, cpu = smp_processor_id();  in mce_amd_feature_init()  local
649 	for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) {  in mce_amd_feature_init()
651 			smca_configure(bank, cpu);  in mce_amd_feature_init()
653 		disable_err_thresholding(c, bank);  in mce_amd_feature_init()
656 			address = get_block_address(address, low, high, bank, block, cpu);  in mce_amd_feature_init()
670 			offset = prepare_threshold_block(bank, block, address, offset, high);  in mce_amd_feature_init()
884 		return smca_get_bank_type(m->bank) == SMCA_UMC && xec == 0x0;  in amd_mce_is_memory_error()
886 	return m->bank == 4 && xec == 0x8;  in amd_mce_is_memory_error()
889 static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc)  in __log_error()  argument
897 	m.bank   = bank;  in __log_error()
915 		rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m.ipid);  in __log_error()
918 			rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m.synd);  in __log_error()
937 _log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc)  in _log_error_bank()  argument
948 	__log_error(bank, status, addr, misc);  in _log_error_bank()
964 static void log_error_deferred(unsigned int bank)  in log_error_deferred()  argument
968 	defrd = _log_error_bank(bank, msr_ops.status(bank),  in log_error_deferred()
969 					msr_ops.addr(bank), 0);  in log_error_deferred()
976 		wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0);  in log_error_deferred()
984 	_log_error_bank(bank, MSR_AMD64_SMCA_MCx_DESTAT(bank),  in log_error_deferred()
985 			      MSR_AMD64_SMCA_MCx_DEADDR(bank), 0);  in log_error_deferred()
991 	unsigned int bank;  in amd_deferred_error_interrupt()  local
993 	for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank)  in amd_deferred_error_interrupt()
994 		log_error_deferred(bank);  in amd_deferred_error_interrupt()
997 static void log_error_thresholding(unsigned int bank, u64 misc)  in log_error_thresholding()  argument
999 	_log_error_bank(bank, msr_ops.status(bank), msr_ops.addr(bank), misc);  in log_error_thresholding()
1017 	log_error_thresholding(block->bank, ((u64)high << 32) | low);  in log_and_reset_block()
1033 	unsigned int bank, cpu = smp_processor_id();  in amd_threshold_interrupt()  local
1036 	 * Validate that the threshold bank has been initialized already. The  in amd_threshold_interrupt()
1043 	for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) {  in amd_threshold_interrupt()
1044 		if (!(per_cpu(bank_map, cpu) & (1 << bank)))  in amd_threshold_interrupt()
1047 		first_block = bp[bank]->blocks;  in amd_threshold_interrupt()
1200 static const char *get_name(unsigned int bank, struct threshold_block *b)  in get_name()  argument
1205 		if (b && bank == 4)  in get_name()
1208 		return th_names[bank];  in get_name()
1211 	bank_type = smca_get_bank_type(bank);  in get_name()
1221 	if (smca_banks[bank].hwid->count == 1)  in get_name()
1226 			  smca_banks[bank].sysfs_id);  in get_name()
1231 				     unsigned int bank, unsigned int block,  in allocate_threshold_blocks()  argument
1238 	if ((bank >= this_cpu_read(mce_num_banks)) || (block >= NR_BLOCKS))  in allocate_threshold_blocks()
1260 	b->bank			= bank;  in allocate_threshold_blocks()
1264 	b->interrupt_capable	= lvt_interrupt_supported(bank, high);  in allocate_threshold_blocks()
1282 	err = kobject_init_and_add(&b->kobj, &threshold_ktype, tb->kobj, get_name(bank, b));  in allocate_threshold_blocks()
1286 	address = get_block_address(address, low, high, bank, ++block, cpu);  in allocate_threshold_blocks()
1290 	err = allocate_threshold_blocks(cpu, tb, bank, block, address);  in allocate_threshold_blocks()
1332 				 unsigned int bank)  in threshold_create_bank()  argument
1337 	const char *name = get_name(bank, NULL);  in threshold_create_bank()
1343 	if (is_shared_bank(bank)) {  in threshold_create_bank()
1354 			bp[bank] = b;  in threshold_create_bank()
1369 	/* Associate the bank with the per-CPU MCE device */  in threshold_create_bank()
1376 	if (is_shared_bank(bank)) {  in threshold_create_bank()
1387 	err = allocate_threshold_blocks(cpu, b, bank, 0, msr_ops.misc(bank));  in threshold_create_bank()
1391 	bp[bank] = b;  in threshold_create_bank()
1407 static void deallocate_threshold_blocks(struct threshold_bank *bank)  in deallocate_threshold_blocks()  argument
1411 	list_for_each_entry_safe(pos, tmp, &bank->blocks->miscj, miscj) {  in deallocate_threshold_blocks()
1416 	kobject_put(&bank->blocks->kobj);  in deallocate_threshold_blocks()
1430 static void threshold_remove_bank(struct threshold_bank *bank)  in threshold_remove_bank()  argument
1434 	if (!bank->blocks)  in threshold_remove_bank()
1437 	if (!bank->shared)  in threshold_remove_bank()
1440 	if (!refcount_dec_and_test(&bank->cpus)) {  in threshold_remove_bank()
1441 		__threshold_remove_blocks(bank);  in threshold_remove_bank()
1445 		 * The last CPU on this node using the shared bank is going  in threshold_remove_bank()
1446 		 * away, remove that bank now.  in threshold_remove_bank()
1453 	deallocate_threshold_blocks(bank);  in threshold_remove_bank()
1456 	kobject_put(bank->kobj);  in threshold_remove_bank()
1457 	kfree(bank);  in threshold_remove_bank()
1463 	unsigned int bank, numbanks = this_cpu_read(mce_num_banks);  in mce_threshold_remove_device()  local
1474 	for (bank = 0; bank < numbanks; bank++) {  in mce_threshold_remove_device()
1475 		if (bp[bank]) {  in mce_threshold_remove_device()
1476 			threshold_remove_bank(bp[bank]);  in mce_threshold_remove_device()
1477 			bp[bank] = NULL;  in mce_threshold_remove_device()
1497 	unsigned int numbanks, bank;  in mce_threshold_create_device()  local
1513 	for (bank = 0; bank < numbanks; ++bank) {  in mce_threshold_create_device()
1514 		if (!(this_cpu_read(bank_map) & (1 << bank)))  in mce_threshold_create_device()
1516 		err = threshold_create_bank(bp, cpu, bank);  in mce_threshold_create_device()