125 	[GDT_ENTRY_KERNEL32_CS]		= GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
126 	[GDT_ENTRY_KERNEL_CS]		= GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
127 	[GDT_ENTRY_KERNEL_DS]		= GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
128 	[GDT_ENTRY_DEFAULT_USER32_CS]	= GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
129 	[GDT_ENTRY_DEFAULT_USER_DS]	= GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
130 	[GDT_ENTRY_DEFAULT_USER_CS]	= GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
132 	[GDT_ENTRY_KERNEL_CS]		= GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
133 	[GDT_ENTRY_KERNEL_DS]		= GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
134 	[GDT_ENTRY_DEFAULT_USER_CS]	= GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
135 	[GDT_ENTRY_DEFAULT_USER_DS]	= GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
142 	[GDT_ENTRY_PNPBIOS_CS32]	= GDT_ENTRY_INIT(0x409a, 0, 0xffff),
144 	[GDT_ENTRY_PNPBIOS_CS16]	= GDT_ENTRY_INIT(0x009a, 0, 0xffff),
146 	[GDT_ENTRY_PNPBIOS_DS]		= GDT_ENTRY_INIT(0x0092, 0, 0xffff),
148 	[GDT_ENTRY_PNPBIOS_TS1]		= GDT_ENTRY_INIT(0x0092, 0, 0),
150 	[GDT_ENTRY_PNPBIOS_TS2]		= GDT_ENTRY_INIT(0x0092, 0, 0),
156 	[GDT_ENTRY_APMBIOS_BASE]	= GDT_ENTRY_INIT(0x409a, 0, 0xffff),
158 	[GDT_ENTRY_APMBIOS_BASE+1]	= GDT_ENTRY_INIT(0x009a, 0, 0xffff),
160 	[GDT_ENTRY_APMBIOS_BASE+2]	= GDT_ENTRY_INIT(0x4092, 0, 0xffff),
162 	[GDT_ENTRY_ESPFIX_SS]		= GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
163 	[GDT_ENTRY_PERCPU]		= GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
178 		return 0;  in x86_nopcid_setup()
182 	return 0;  in x86_nopcid_setup()
195 		return 0;  in x86_noinvpcid_setup()
199 	return 0;  in x86_noinvpcid_setup()
235 		      "popl %0		\n\t"  in flag_is_changeable_p()
236 		      "movl %0, %1	\n\t"  in flag_is_changeable_p()
237 		      "xorl %2, %0	\n\t"  in flag_is_changeable_p()
238 		      "pushl %0		\n\t"  in flag_is_changeable_p()
241 		      "popl %0		\n\t"  in flag_is_changeable_p()
247 	return ((f1^f2) & flag) != 0;  in flag_is_changeable_p()
266 	lo |= 0x200000;  in squash_the_stupid_serial_number()
273 	c->cpuid_level = cpuid_eax(0);  in squash_the_stupid_serial_number()
278 	disable_x86_serial_nr = 0;  in x86_serial_nr_setup()
360 	unsigned long bits_missing = 0;  in native_write_cr0()
363 	asm volatile("mov %0,%%cr0": "+r" (val) : : "memory");  in native_write_cr0()
379 	unsigned long bits_changed = 0;  in native_write_cr4()
382 	asm volatile("mov %0,%%cr4": "+r" (val) : : "memory");  in native_write_cr4()
391 		WARN_ONCE(bits_changed, "pinned CR4 bits changed: 0x%lx!?\n",  in native_write_cr4()
450 		return 0;  in x86_nofsgsbase_setup()
525 	{ X86_FEATURE_MWAIT,		0x00000005 },
526 	{ X86_FEATURE_DCA,		0x00000009 },
527 	{ X86_FEATURE_XSAVE,		0x0000000d },
528 	{ 0, 0 }
541 		 * extended_extended_level is set to 0 if unavailable  in filter_cpuid_features()
546 		if (!((s32)df->level < 0 ?  in filter_cpuid_features()
555 		pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",  in filter_cpuid_features()
563  * in particular, if CPUID levels 0x80000002..4 are supported, this
599 	__loadsegment_simple(gs, 0);  in load_percpu_segment()
651 	if (c->extended_cpuid_level < 0x80000004)  in get_model_name()
655 	cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);  in get_model_name()
656 	cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);  in get_model_name()
657 	cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);  in get_model_name()
658 	c->x86_model_id[48] = 0;  in get_model_name()
661 	p = q = s = &c->x86_model_id[0];  in get_model_name()
674 	*(s + 1) = '\0';  in get_model_name()
685 	cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);  in detect_num_cpu_cores()
686 	if (eax & 0x1f)  in detect_num_cpu_cores()
696 	if (n >= 0x80000005) {  in cpu_detect_cache_sizes()
697 		cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);  in cpu_detect_cache_sizes()
701 		c->x86_tlbsize = 0;  in cpu_detect_cache_sizes()
705 	if (n < 0x80000006)	/* Some chips just has a large L1. */  in cpu_detect_cache_sizes()
708 	cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);  in cpu_detect_cache_sizes()
712 	c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);  in cpu_detect_cache_sizes()
722 	if (l2size == 0)  in cpu_detect_cache_sizes()
767 	smp_num_siblings = (ebx & 0xff0000) >> 16;  in detect_ht_early()
771 	return 0;  in detect_ht_early()
779 	if (detect_ht_early(c) < 0)  in detect_ht()
801 	for (i = 0; i < X86_VENDOR_NUM; i++) {  in get_cpu_vendor()
805 		if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||  in get_cpu_vendor()
825 	cpuid(0x00000000, (unsigned int *)&c->cpuid_level,  in cpu_detect()
826 	      (unsigned int *)&c->x86_vendor_id[0],  in cpu_detect()
831 	/* Intel-defined flags: level 0x00000001 */  in cpu_detect()
832 	if (c->cpuid_level >= 0x00000001) {  in cpu_detect()
835 		cpuid(0x00000001, &tfms, &misc, &junk, &cap0);  in cpu_detect()
841 			c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;  in cpu_detect()
851 	for (i = 0; i < NCAPINTS + NBUGINTS; i++) {  in apply_forced_caps()
902 	/* Intel-defined flags: level 0x00000001 */  in get_cpu_cap()
903 	if (c->cpuid_level >= 0x00000001) {  in get_cpu_cap()
904 		cpuid(0x00000001, &eax, &ebx, &ecx, &edx);  in get_cpu_cap()
910 	/* Thermal and Power Management Leaf: level 0x00000006 (eax) */  in get_cpu_cap()
911 	if (c->cpuid_level >= 0x00000006)  in get_cpu_cap()
912 		c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);  in get_cpu_cap()
914 	/* Additional Intel-defined flags: level 0x00000007 */  in get_cpu_cap()
915 	if (c->cpuid_level >= 0x00000007) {  in get_cpu_cap()
916 		cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);  in get_cpu_cap()
923 			cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx);  in get_cpu_cap()
928 	/* Extended state features: level 0x0000000d */  in get_cpu_cap()
929 	if (c->cpuid_level >= 0x0000000d) {  in get_cpu_cap()
930 		cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);  in get_cpu_cap()
935 	/* AMD-defined flags: level 0x80000001 */  in get_cpu_cap()
936 	eax = cpuid_eax(0x80000000);  in get_cpu_cap()
939 	if ((eax & 0xffff0000) == 0x80000000) {  in get_cpu_cap()
940 		if (eax >= 0x80000001) {  in get_cpu_cap()
941 			cpuid(0x80000001, &eax, &ebx, &ecx, &edx);  in get_cpu_cap()
948 	if (c->extended_cpuid_level >= 0x80000007) {  in get_cpu_cap()
949 		cpuid(0x80000007, &eax, &ebx, &ecx, &edx);  in get_cpu_cap()
955 	if (c->extended_cpuid_level >= 0x80000008) {  in get_cpu_cap()
956 		cpuid(0x80000008, &eax, &ebx, &ecx, &edx);  in get_cpu_cap()
960 	if (c->extended_cpuid_level >= 0x8000000a)  in get_cpu_cap()
961 		c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);  in get_cpu_cap()
978 	if (c->extended_cpuid_level >= 0x80000008) {  in get_cpu_address_sizes()
979 		cpuid(0x80000008, &eax, &ebx, &ecx, &edx);  in get_cpu_address_sizes()
981 		c->x86_virt_bits = (eax >> 8) & 0xff;  in get_cpu_address_sizes()
982 		c->x86_phys_bits = eax & 0xff;  in get_cpu_address_sizes()
1005 	for (i = 0; i < X86_VENDOR_NUM; i++)  in identify_cpu_without_cpuid()
1007 			c->x86_vendor_id[0] = 0;  in identify_cpu_without_cpuid()
1009 			if (c->x86_vendor_id[0]) {  in identify_cpu_without_cpuid()
1017 #define NO_SPECULATION		BIT(0)
1078 	/* AMD Family 0xf - 0x12 */
1079 	VULNWL_AMD(0x0f,	NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1080 	VULNWL_AMD(0x10,	NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1081 	VULNWL_AMD(0x11,	NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1082 	VULNWL_AMD(0x12,	NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1084 	/* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
1099 #define SRBDS		BIT(0)
1110 	VULNBL_INTEL_STEPPINGS(KABYLAKE_L,	X86_STEPPINGS(0x0, 0xC),	SRBDS),
1111 	VULNBL_INTEL_STEPPINGS(KABYLAKE,	X86_STEPPINGS(0x0, 0xD),	SRBDS),
1124 	u64 ia32_cap = 0;  in x86_read_arch_cap_msr()
1168 	 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when:  in cpu_set_bug_bits()
1256 	if (arglen <= 0)  in cpu_parse_early_param()
1262 		if (res == 0 || res == 3)  in cpu_parse_early_param()
1269 		if (bit >= 0 && bit < NCAPINTS * 32) {  in cpu_parse_early_param()
1299 	memset(&c->x86_capability, 0, sizeof(c->x86_capability));  in early_identify_cpu()
1300 	c->extended_cpuid_level = 0;  in early_identify_cpu()
1317 		c->cpu_index = 0;  in early_identify_cpu()
1363 	int count = 0;  in early_cpu_init()
1381 			for (j = 0; j < 2; j++) {  in early_cpu_init()
1414 	loadsegment(fs, 0);  in detect_null_seg_behavior()
1416 	if (tmp != 0)  in detect_null_seg_behavior()
1424 	c->extended_cpuid_level = 0;  in generic_identify()
1441 	if (c->cpuid_level >= 0x00000001) {  in generic_identify()
1442 		c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;  in generic_identify()
1445 		c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);  in generic_identify()
1459 	 * systems that run Linux at CPL > 0 may or may not have the  in generic_identify()
1493 	c->logical_proc_id = 0;  in validate_apic_and_package_id()
1505 	c->x86_cache_size = 0;  in identify_cpu()
1507 	c->x86_model = c->x86_stepping = 0;	/* So far unknown... */  in identify_cpu()
1508 	c->x86_vendor_id[0] = '\0'; /* Unset */  in identify_cpu()
1509 	c->x86_model_id[0] = '\0';  /* Unset */  in identify_cpu()
1511 	c->x86_coreid_bits = 0;  in identify_cpu()
1512 	c->cu_id = 0xff;  in identify_cpu()
1524 	memset(&c->x86_capability, 0, sizeof(c->x86_capability));  in identify_cpu()
1526 	memset(&c->vmx_capability, 0, sizeof(c->vmx_capability));  in identify_cpu()
1538 	c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);  in identify_cpu()
1577 	if (!c->x86_model_id[0]) {  in identify_cpu()
1609 		for (i = 0; i < NCAPINTS; i++)  in identify_cpu()
1649 	wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);  in enable_sep_cpu()
1650 	wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0);  in enable_sep_cpu()
1651 	wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);  in enable_sep_cpu()
1698 		if (c->cpuid_level >= 0)  in print_cpu_info()
1705 	if (c->x86_model_id[0])  in print_cpu_info()
1710 	pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);  in print_cpu_info()
1712 	if (c->x86_stepping || c->cpuid_level >= 0)  in print_cpu_info()
1713 		pr_cont(", stepping: 0x%x)\n", c->x86_stepping);  in print_cpu_info()
1751 	wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);  in syscall_init()
1769 	wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);  in syscall_init()
1770 	wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);  in syscall_init()
1808 	for (i = 0; i < 8; i++) {  in clear_all_debug_regs()
1813 		set_debugreg(0, i);  in clear_all_debug_regs()
1901 	tss->io_bitmap.prev_max = 0;  in tss_setup_io_bitmap()
1902 	tss->io_bitmap.prev_sequence = 0;  in tss_setup_io_bitmap()
1903 	memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap));  in tss_setup_io_bitmap()
1908 	tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL;  in tss_setup_io_bitmap()
1952 	if (this_cpu_read(numa_node) == 0 &&  in cpu_init()
1972 		loadsegment(fs, 0);  in cpu_init()
1973 		memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);  in cpu_init()
1976 		wrmsrl(MSR_FS_BASE, 0);  in cpu_init()
1977 		wrmsrl(MSR_KERNEL_GS_BASE, 0);  in cpu_init()
2028 	info.cpuid_level = cpuid_eax(0);  in microcode_check()