Lines Matching +full:8 +full:- +full:cpu
1 // SPDX-License-Identifier: GPL-2.0
3 * Routines to identify caches on Intel CPU.
7 * Ashok Raj <ashok.raj@intel.com>: Work with CPU hotplug infrastructure.
13 #include <linux/cpu.h>
24 #include "cpu.h"
45 { 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
46 { 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */
47 { 0x09, LVL_1_INST, 32 }, /* 4-way set assoc, 64 byte line size */
48 { 0x0a, LVL_1_DATA, 8 }, /* 2 way set assoc, 32 byte line size */
49 { 0x0c, LVL_1_DATA, 16 }, /* 4-way set assoc, 32 byte line size */
50 { 0x0d, LVL_1_DATA, 16 }, /* 4-way set assoc, 64 byte line size */
51 { 0x0e, LVL_1_DATA, 24 }, /* 6-way set assoc, 64 byte line size */
52 { 0x21, LVL_2, 256 }, /* 8-way set assoc, 64 byte line size */
53 { 0x22, LVL_3, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */
54 { 0x23, LVL_3, MB(1) }, /* 8-way set assoc, sectored cache, 64 byte line size */
55 { 0x25, LVL_3, MB(2) }, /* 8-way set assoc, sectored cache, 64 byte line size */
56 { 0x29, LVL_3, MB(4) }, /* 8-way set assoc, sectored cache, 64 byte line size */
57 { 0x2c, LVL_1_DATA, 32 }, /* 8-way set assoc, 64 byte line size */
58 { 0x30, LVL_1_INST, 32 }, /* 8-way set assoc, 64 byte line size */
59 { 0x39, LVL_2, 128 }, /* 4-way set assoc, sectored cache, 64 byte line size */
60 { 0x3a, LVL_2, 192 }, /* 6-way set assoc, sectored cache, 64 byte line size */
61 { 0x3b, LVL_2, 128 }, /* 2-way set assoc, sectored cache, 64 byte line size */
62 { 0x3c, LVL_2, 256 }, /* 4-way set assoc, sectored cache, 64 byte line size */
63 { 0x3d, LVL_2, 384 }, /* 6-way set assoc, sectored cache, 64 byte line size */
64 { 0x3e, LVL_2, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */
65 { 0x3f, LVL_2, 256 }, /* 2-way set assoc, 64 byte line size */
66 { 0x41, LVL_2, 128 }, /* 4-way set assoc, 32 byte line size */
67 { 0x42, LVL_2, 256 }, /* 4-way set assoc, 32 byte line size */
68 { 0x43, LVL_2, 512 }, /* 4-way set assoc, 32 byte line size */
69 { 0x44, LVL_2, MB(1) }, /* 4-way set assoc, 32 byte line size */
70 { 0x45, LVL_2, MB(2) }, /* 4-way set assoc, 32 byte line size */
71 { 0x46, LVL_3, MB(4) }, /* 4-way set assoc, 64 byte line size */
72 { 0x47, LVL_3, MB(8) }, /* 8-way set assoc, 64 byte line size */
73 { 0x48, LVL_2, MB(3) }, /* 12-way set assoc, 64 byte line size */
74 { 0x49, LVL_3, MB(4) }, /* 16-way set assoc, 64 byte line size */
75 { 0x4a, LVL_3, MB(6) }, /* 12-way set assoc, 64 byte line size */
76 { 0x4b, LVL_3, MB(8) }, /* 16-way set assoc, 64 byte line size */
77 { 0x4c, LVL_3, MB(12) }, /* 12-way set assoc, 64 byte line size */
78 { 0x4d, LVL_3, MB(16) }, /* 16-way set assoc, 64 byte line size */
79 { 0x4e, LVL_2, MB(6) }, /* 24-way set assoc, 64 byte line size */
80 { 0x60, LVL_1_DATA, 16 }, /* 8-way set assoc, sectored cache, 64 byte line size */
81 { 0x66, LVL_1_DATA, 8 }, /* 4-way set assoc, sectored cache, 64 byte line size */
82 { 0x67, LVL_1_DATA, 16 }, /* 4-way set assoc, sectored cache, 64 byte line size */
83 { 0x68, LVL_1_DATA, 32 }, /* 4-way set assoc, sectored cache, 64 byte line size */
84 { 0x70, LVL_TRACE, 12 }, /* 8-way set assoc */
85 { 0x71, LVL_TRACE, 16 }, /* 8-way set assoc */
86 { 0x72, LVL_TRACE, 32 }, /* 8-way set assoc */
87 { 0x73, LVL_TRACE, 64 }, /* 8-way set assoc */
88 { 0x78, LVL_2, MB(1) }, /* 4-way set assoc, 64 byte line size */
89 { 0x79, LVL_2, 128 }, /* 8-way set assoc, sectored cache, 64 byte line size */
90 { 0x7a, LVL_2, 256 }, /* 8-way set assoc, sectored cache, 64 byte line size */
91 { 0x7b, LVL_2, 512 }, /* 8-way set assoc, sectored cache, 64 byte line size */
92 { 0x7c, LVL_2, MB(1) }, /* 8-way set assoc, sectored cache, 64 byte line size */
93 { 0x7d, LVL_2, MB(2) }, /* 8-way set assoc, 64 byte line size */
94 { 0x7f, LVL_2, 512 }, /* 2-way set assoc, 64 byte line size */
95 { 0x80, LVL_2, 512 }, /* 8-way set assoc, 64 byte line size */
96 { 0x82, LVL_2, 256 }, /* 8-way set assoc, 32 byte line size */
97 { 0x83, LVL_2, 512 }, /* 8-way set assoc, 32 byte line size */
98 { 0x84, LVL_2, MB(1) }, /* 8-way set assoc, 32 byte line size */
99 { 0x85, LVL_2, MB(2) }, /* 8-way set assoc, 32 byte line size */
100 { 0x86, LVL_2, 512 }, /* 4-way set assoc, 64 byte line size */
101 { 0x87, LVL_2, MB(1) }, /* 8-way set assoc, 64 byte line size */
102 { 0xd0, LVL_3, 512 }, /* 4-way set assoc, 64 byte line size */
103 { 0xd1, LVL_3, MB(1) }, /* 4-way set assoc, 64 byte line size */
104 { 0xd2, LVL_3, MB(2) }, /* 4-way set assoc, 64 byte line size */
105 { 0xd6, LVL_3, MB(1) }, /* 8-way set assoc, 64 byte line size */
106 { 0xd7, LVL_3, MB(2) }, /* 8-way set assoc, 64 byte line size */
107 { 0xd8, LVL_3, MB(4) }, /* 12-way set assoc, 64 byte line size */
108 { 0xdc, LVL_3, MB(2) }, /* 12-way set assoc, 64 byte line size */
109 { 0xdd, LVL_3, MB(4) }, /* 12-way set assoc, 64 byte line size */
110 { 0xde, LVL_3, MB(8) }, /* 12-way set assoc, 64 byte line size */
111 { 0xe2, LVL_3, MB(2) }, /* 16-way set assoc, 64 byte line size */
112 { 0xe3, LVL_3, MB(4) }, /* 16-way set assoc, 64 byte line size */
113 { 0xe4, LVL_3, MB(8) }, /* 16-way set assoc, 64 byte line size */
114 { 0xea, LVL_3, MB(12) }, /* 24-way set assoc, 64 byte line size */
115 { 0xeb, LVL_3, MB(18) }, /* 24-way set assoc, 64 byte line size */
116 { 0xec, LVL_3, MB(24) }, /* 24-way set assoc, 64 byte line size */
176 unsigned line_size:8;
177 unsigned lines_per_tag:8;
178 unsigned assoc:8;
179 unsigned size_in_kb:8;
186 unsigned line_size:8;
196 unsigned line_size:8;
209 [6] = 8,
210 [8] = 16,
216 [0xf] = 0xffff /* fully associative - no way to show this currently */
241 eax->full = 0; in amd_cpuid4()
242 ebx->full = 0; in amd_cpuid4()
243 ecx->full = 0; in amd_cpuid4()
253 if (!l1->val) in amd_cpuid4()
255 assoc = assocs[l1->assoc]; in amd_cpuid4()
256 line_size = l1->line_size; in amd_cpuid4()
257 lines_per_tag = l1->lines_per_tag; in amd_cpuid4()
258 size_in_kb = l1->size_in_kb; in amd_cpuid4()
285 eax->split.is_self_initializing = 1; in amd_cpuid4()
286 eax->split.type = types[leaf]; in amd_cpuid4()
287 eax->split.level = levels[leaf]; in amd_cpuid4()
288 eax->split.num_threads_sharing = 0; in amd_cpuid4()
289 eax->split.num_cores_on_die = __this_cpu_read(cpu_info.x86_max_cores) - 1; in amd_cpuid4()
293 eax->split.is_fully_associative = 1; in amd_cpuid4()
294 ebx->split.coherency_line_size = line_size - 1; in amd_cpuid4()
295 ebx->split.ways_of_associativity = assoc - 1; in amd_cpuid4()
296 ebx->split.physical_line_partition = lines_per_tag - 1; in amd_cpuid4()
297 ecx->split.number_of_sets = (size_in_kb * 1024) / line_size / in amd_cpuid4()
298 (ebx->split.ways_of_associativity + 1) - 1; in amd_cpuid4()
308 struct amd_l3_cache *l3 = &nb->l3_cache; in amd_calc_l3_indices()
312 pci_read_config_dword(nb->misc, 0x1C4, &val); in amd_calc_l3_indices()
315 l3->subcaches[0] = sc0 = !(val & BIT(0)); in amd_calc_l3_indices()
316 l3->subcaches[1] = sc1 = !(val & BIT(4)); in amd_calc_l3_indices()
319 l3->subcaches[0] = sc0 += !(val & BIT(1)); in amd_calc_l3_indices()
320 l3->subcaches[1] = sc1 += !(val & BIT(5)); in amd_calc_l3_indices()
323 l3->subcaches[2] = sc2 = !(val & BIT(8)) + !(val & BIT(9)); in amd_calc_l3_indices()
324 l3->subcaches[3] = sc3 = !(val & BIT(12)) + !(val & BIT(13)); in amd_calc_l3_indices()
326 l3->indices = (max(max3(sc0, sc1, sc2), sc3) << 10) - 1; in amd_calc_l3_indices()
340 pci_read_config_dword(nb->misc, 0x1BC + slot * 4, ®); in amd_get_l3_disable_slot()
346 return -1; in amd_get_l3_disable_slot()
353 struct amd_northbridge *nb = this_leaf->priv; in show_cache_disable()
373 static void amd_l3_disable_index(struct amd_northbridge *nb, int cpu, in amd_l3_disable_index() argument
386 if (!nb->l3_cache.subcaches[i]) in amd_l3_disable_index()
389 pci_write_config_dword(nb->misc, 0x1BC + slot * 4, reg); in amd_l3_disable_index()
396 wbinvd_on_cpu(cpu); in amd_l3_disable_index()
399 pci_write_config_dword(nb->misc, 0x1BC + slot * 4, reg); in amd_l3_disable_index()
404 * disable a L3 cache index by using a disable-slot
407 * @cpu: A CPU on the node containing the L3 cache
413 static int amd_set_l3_disable_slot(struct amd_northbridge *nb, int cpu, in amd_set_l3_disable_slot() argument
421 return -EEXIST; in amd_set_l3_disable_slot()
423 if (index > nb->l3_cache.indices) in amd_set_l3_disable_slot()
424 return -EINVAL; in amd_set_l3_disable_slot()
428 return -EEXIST; in amd_set_l3_disable_slot()
430 amd_l3_disable_index(nb, cpu, slot, index); in amd_set_l3_disable_slot()
440 int cpu, err = 0; in store_cache_disable() local
441 struct amd_northbridge *nb = this_leaf->priv; in store_cache_disable()
444 return -EPERM; in store_cache_disable()
446 cpu = cpumask_first(&this_leaf->shared_cpu_map); in store_cache_disable()
449 return -EINVAL; in store_cache_disable()
451 err = amd_set_l3_disable_slot(nb, cpu, slot, val); in store_cache_disable()
453 if (err == -EEXIST) in store_cache_disable()
477 int cpu = cpumask_first(&this_leaf->shared_cpu_map); in subcaches_show() local
479 return sprintf(buf, "%x\n", amd_get_subcaches(cpu)); in subcaches_show()
487 int cpu = cpumask_first(&this_leaf->shared_cpu_map); in subcaches_store() local
491 return -EPERM; in subcaches_store()
494 return -EINVAL; in subcaches_store()
496 if (amd_set_subcaches(cpu, val)) in subcaches_store()
497 return -EINVAL; in subcaches_store()
512 umode_t mode = attr->mode; in cache_private_attrs_is_visible()
514 if (!this_leaf->priv) in cache_private_attrs_is_visible()
564 struct amd_northbridge *nb = this_leaf->priv; in cache_get_priv_group()
566 if (this_leaf->level < 3 || !nb) in cache_get_priv_group()
569 if (nb && nb->l3_cache.indices) in cache_get_priv_group()
584 this_leaf->nb = node_to_amd_nb(node); in amd_init_l3_cache()
585 if (this_leaf->nb && !this_leaf->nb->l3_cache.indices) in amd_init_l3_cache()
586 amd_calc_l3_indices(this_leaf->nb); in amd_init_l3_cache()
616 return -EIO; /* better error ? */ in cpuid4_cache_lookup_regs()
618 this_leaf->eax = eax; in cpuid4_cache_lookup_regs()
619 this_leaf->ebx = ebx; in cpuid4_cache_lookup_regs()
620 this_leaf->ecx = ecx; in cpuid4_cache_lookup_regs()
621 this_leaf->size = (ecx.split.number_of_sets + 1) * in cpuid4_cache_lookup_regs()
632 int i = -1; in find_num_cache_leaves()
634 if (c->x86_vendor == X86_VENDOR_AMD || in find_num_cache_leaves()
635 c->x86_vendor == X86_VENDOR_HYGON) in find_num_cache_leaves()
649 void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, int cpu, u8 node_id) in cacheinfo_amd_init_llc_id() argument
658 if (c->x86 < 0x17) { in cacheinfo_amd_init_llc_id()
660 per_cpu(cpu_llc_id, cpu) = node_id; in cacheinfo_amd_init_llc_id()
661 } else if (c->x86 == 0x17 && c->x86_model <= 0x1F) { in cacheinfo_amd_init_llc_id()
666 per_cpu(cpu_llc_id, cpu) = c->apicid >> 3; in cacheinfo_amd_init_llc_id()
673 u32 llc_index = find_num_cache_leaves(c) - 1; in cacheinfo_amd_init_llc_id()
682 per_cpu(cpu_llc_id, cpu) = c->apicid >> bits; in cacheinfo_amd_init_llc_id()
687 void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c, int cpu, u8 node_id) in cacheinfo_hygon_init_llc_id() argument
700 per_cpu(cpu_llc_id, cpu) = c->apicid >> 3; in cacheinfo_hygon_init_llc_id()
708 } else if (c->extended_cpuid_level >= 0x80000006) { in init_amd_cacheinfo()
729 unsigned int cpu = c->cpu_index; in init_intel_cacheinfo() local
732 if (c->cpuid_level > 3) { in init_intel_cacheinfo()
736 /* Init num_cache_leaves from boot CPU */ in init_intel_cacheinfo()
764 l2_id = c->apicid & ~((1 << index_msb) - 1); in init_intel_cacheinfo()
770 l3_id = c->apicid & ~((1 << index_msb) - 1); in init_intel_cacheinfo()
781 if ((num_cache_leaves == 0 || c->x86 == 15) && c->cpuid_level > 1) { in init_intel_cacheinfo()
788 if (num_cache_leaves != 0 && c->x86 == 15) in init_intel_cacheinfo()
848 per_cpu(cpu_llc_id, cpu) = l2_id; in init_intel_cacheinfo()
855 per_cpu(cpu_llc_id, cpu) = l3_id; in init_intel_cacheinfo()
865 * c->phys_proc_id. in init_intel_cacheinfo()
867 if (per_cpu(cpu_llc_id, cpu) == BAD_APICID) in init_intel_cacheinfo()
868 per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; in init_intel_cacheinfo()
871 c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i+l1d)); in init_intel_cacheinfo()
877 static int __cache_amd_cpumap_setup(unsigned int cpu, int index, in __cache_amd_cpumap_setup() argument
880 struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); in __cache_amd_cpumap_setup()
885 * For L3, always use the pre-calculated cpu_llc_shared_mask in __cache_amd_cpumap_setup()
889 for_each_cpu(i, cpu_llc_shared_mask(cpu)) { in __cache_amd_cpumap_setup()
891 if (!this_cpu_ci->info_list) in __cache_amd_cpumap_setup()
893 this_leaf = this_cpu_ci->info_list + index; in __cache_amd_cpumap_setup()
894 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) { in __cache_amd_cpumap_setup()
898 &this_leaf->shared_cpu_map); in __cache_amd_cpumap_setup()
904 nshared = base->eax.split.num_threads_sharing + 1; in __cache_amd_cpumap_setup()
905 apicid = cpu_data(cpu).apicid; in __cache_amd_cpumap_setup()
906 first = apicid - (apicid % nshared); in __cache_amd_cpumap_setup()
907 last = first + nshared - 1; in __cache_amd_cpumap_setup()
911 if (!this_cpu_ci->info_list) in __cache_amd_cpumap_setup()
918 this_leaf = this_cpu_ci->info_list + index; in __cache_amd_cpumap_setup()
925 &this_leaf->shared_cpu_map); in __cache_amd_cpumap_setup()
934 static void __cache_cpumap_setup(unsigned int cpu, int index, in __cache_cpumap_setup() argument
937 struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); in __cache_cpumap_setup()
941 struct cpuinfo_x86 *c = &cpu_data(cpu); in __cache_cpumap_setup()
943 if (c->x86_vendor == X86_VENDOR_AMD || in __cache_cpumap_setup()
944 c->x86_vendor == X86_VENDOR_HYGON) { in __cache_cpumap_setup()
945 if (__cache_amd_cpumap_setup(cpu, index, base)) in __cache_cpumap_setup()
949 this_leaf = this_cpu_ci->info_list + index; in __cache_cpumap_setup()
950 num_threads_sharing = 1 + base->eax.split.num_threads_sharing; in __cache_cpumap_setup()
952 cpumask_set_cpu(cpu, &this_leaf->shared_cpu_map); in __cache_cpumap_setup()
959 if (cpu_data(i).apicid >> index_msb == c->apicid >> index_msb) { in __cache_cpumap_setup()
962 if (i == cpu || !sib_cpu_ci->info_list) in __cache_cpumap_setup()
964 sibling_leaf = sib_cpu_ci->info_list + index; in __cache_cpumap_setup()
965 cpumask_set_cpu(i, &this_leaf->shared_cpu_map); in __cache_cpumap_setup()
966 cpumask_set_cpu(cpu, &sibling_leaf->shared_cpu_map); in __cache_cpumap_setup()
973 this_leaf->id = base->id; in ci_leaf_init()
974 this_leaf->attributes = CACHE_ID; in ci_leaf_init()
975 this_leaf->level = base->eax.split.level; in ci_leaf_init()
976 this_leaf->type = cache_type_map[base->eax.split.type]; in ci_leaf_init()
977 this_leaf->coherency_line_size = in ci_leaf_init()
978 base->ebx.split.coherency_line_size + 1; in ci_leaf_init()
979 this_leaf->ways_of_associativity = in ci_leaf_init()
980 base->ebx.split.ways_of_associativity + 1; in ci_leaf_init()
981 this_leaf->size = base->size; in ci_leaf_init()
982 this_leaf->number_of_sets = base->ecx.split.number_of_sets + 1; in ci_leaf_init()
983 this_leaf->physical_line_partition = in ci_leaf_init()
984 base->ebx.split.physical_line_partition + 1; in ci_leaf_init()
985 this_leaf->priv = base->nb; in ci_leaf_init()
988 static int __init_cache_level(unsigned int cpu) in __init_cache_level() argument
990 struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); in __init_cache_level()
993 return -ENOENT; in __init_cache_level()
995 return -EINVAL; in __init_cache_level()
996 this_cpu_ci->num_levels = 3; in __init_cache_level()
997 this_cpu_ci->num_leaves = num_cache_leaves; in __init_cache_level()
1002 * The max shared threads number comes from CPUID.4:EAX[25-14] with input
1006 static void get_cache_id(int cpu, struct _cpuid4_info_regs *id4_regs) in get_cache_id() argument
1008 struct cpuinfo_x86 *c = &cpu_data(cpu); in get_cache_id()
1012 num_threads_sharing = 1 + id4_regs->eax.split.num_threads_sharing; in get_cache_id()
1014 id4_regs->id = c->apicid >> index_msb; in get_cache_id()
1017 static int __populate_cache_leaves(unsigned int cpu) in __populate_cache_leaves() argument
1020 struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); in __populate_cache_leaves()
1021 struct cacheinfo *this_leaf = this_cpu_ci->info_list; in __populate_cache_leaves()
1024 for (idx = 0; idx < this_cpu_ci->num_leaves; idx++) { in __populate_cache_leaves()
1028 get_cache_id(cpu, &id4_regs); in __populate_cache_leaves()
1030 __cache_cpumap_setup(cpu, idx, &id4_regs); in __populate_cache_leaves()
1032 this_cpu_ci->cpu_map_populated = true; in __populate_cache_leaves()