Lines Matching +full:0 +full:x00000802
20 #define VMCS_CONTROL_BIT(x) BIT(VMX_FEATURE_##x & 0x1f)
47 #define CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x0401e172
83 #define PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x00000016
85 #define VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004
86 #define VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200
87 #define VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000
88 #define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
89 #define VM_EXIT_SAVE_IA32_PAT 0x00040000
90 #define VM_EXIT_LOAD_IA32_PAT 0x00080000
91 #define VM_EXIT_SAVE_IA32_EFER 0x00100000
92 #define VM_EXIT_LOAD_IA32_EFER 0x00200000
93 #define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000
94 #define VM_EXIT_CLEAR_BNDCFGS 0x00800000
95 #define VM_EXIT_PT_CONCEAL_PIP 0x01000000
96 #define VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000
98 #define VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR 0x00036dff
100 #define VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004
101 #define VM_ENTRY_IA32E_MODE 0x00000200
102 #define VM_ENTRY_SMM 0x00000400
103 #define VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800
104 #define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000
105 #define VM_ENTRY_LOAD_IA32_PAT 0x00004000
106 #define VM_ENTRY_LOAD_IA32_EFER 0x00008000
107 #define VM_ENTRY_LOAD_BNDCFGS 0x00010000
108 #define VM_ENTRY_PT_CONCEAL_PIP 0x00020000
109 #define VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000
111 #define VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR 0x000011ff
113 #define VMX_MISC_PREEMPTION_TIMER_RATE_MASK 0x0000001f
114 #define VMX_MISC_SAVE_EFER_LMA 0x00000020
115 #define VMX_MISC_ACTIVITY_HLT 0x00000040
116 #define VMX_MISC_ZERO_LEN_INS 0x40000000
120 #define VMFUNC_CONTROL_BIT(x) BIT((VMX_FEATURE_##x & 0x1f) - 28)
127 return vmx_basic & GENMASK_ULL(30, 0); in vmx_basic_vmcs_revision_id()
157 VIRTUAL_PROCESSOR_ID = 0x00000000,
158 POSTED_INTR_NV = 0x00000002,
159 GUEST_ES_SELECTOR = 0x00000800,
160 GUEST_CS_SELECTOR = 0x00000802,
161 GUEST_SS_SELECTOR = 0x00000804,
162 GUEST_DS_SELECTOR = 0x00000806,
163 GUEST_FS_SELECTOR = 0x00000808,
164 GUEST_GS_SELECTOR = 0x0000080a,
165 GUEST_LDTR_SELECTOR = 0x0000080c,
166 GUEST_TR_SELECTOR = 0x0000080e,
167 GUEST_INTR_STATUS = 0x00000810,
168 GUEST_PML_INDEX = 0x00000812,
169 HOST_ES_SELECTOR = 0x00000c00,
170 HOST_CS_SELECTOR = 0x00000c02,
171 HOST_SS_SELECTOR = 0x00000c04,
172 HOST_DS_SELECTOR = 0x00000c06,
173 HOST_FS_SELECTOR = 0x00000c08,
174 HOST_GS_SELECTOR = 0x00000c0a,
175 HOST_TR_SELECTOR = 0x00000c0c,
176 IO_BITMAP_A = 0x00002000,
177 IO_BITMAP_A_HIGH = 0x00002001,
178 IO_BITMAP_B = 0x00002002,
179 IO_BITMAP_B_HIGH = 0x00002003,
180 MSR_BITMAP = 0x00002004,
181 MSR_BITMAP_HIGH = 0x00002005,
182 VM_EXIT_MSR_STORE_ADDR = 0x00002006,
183 VM_EXIT_MSR_STORE_ADDR_HIGH = 0x00002007,
184 VM_EXIT_MSR_LOAD_ADDR = 0x00002008,
185 VM_EXIT_MSR_LOAD_ADDR_HIGH = 0x00002009,
186 VM_ENTRY_MSR_LOAD_ADDR = 0x0000200a,
187 VM_ENTRY_MSR_LOAD_ADDR_HIGH = 0x0000200b,
188 PML_ADDRESS = 0x0000200e,
189 PML_ADDRESS_HIGH = 0x0000200f,
190 TSC_OFFSET = 0x00002010,
191 TSC_OFFSET_HIGH = 0x00002011,
192 VIRTUAL_APIC_PAGE_ADDR = 0x00002012,
193 VIRTUAL_APIC_PAGE_ADDR_HIGH = 0x00002013,
194 APIC_ACCESS_ADDR = 0x00002014,
195 APIC_ACCESS_ADDR_HIGH = 0x00002015,
196 POSTED_INTR_DESC_ADDR = 0x00002016,
197 POSTED_INTR_DESC_ADDR_HIGH = 0x00002017,
198 VM_FUNCTION_CONTROL = 0x00002018,
199 VM_FUNCTION_CONTROL_HIGH = 0x00002019,
200 EPT_POINTER = 0x0000201a,
201 EPT_POINTER_HIGH = 0x0000201b,
202 EOI_EXIT_BITMAP0 = 0x0000201c,
203 EOI_EXIT_BITMAP0_HIGH = 0x0000201d,
204 EOI_EXIT_BITMAP1 = 0x0000201e,
205 EOI_EXIT_BITMAP1_HIGH = 0x0000201f,
206 EOI_EXIT_BITMAP2 = 0x00002020,
207 EOI_EXIT_BITMAP2_HIGH = 0x00002021,
208 EOI_EXIT_BITMAP3 = 0x00002022,
209 EOI_EXIT_BITMAP3_HIGH = 0x00002023,
210 EPTP_LIST_ADDRESS = 0x00002024,
211 EPTP_LIST_ADDRESS_HIGH = 0x00002025,
212 VMREAD_BITMAP = 0x00002026,
213 VMREAD_BITMAP_HIGH = 0x00002027,
214 VMWRITE_BITMAP = 0x00002028,
215 VMWRITE_BITMAP_HIGH = 0x00002029,
216 XSS_EXIT_BITMAP = 0x0000202C,
217 XSS_EXIT_BITMAP_HIGH = 0x0000202D,
218 ENCLS_EXITING_BITMAP = 0x0000202E,
219 ENCLS_EXITING_BITMAP_HIGH = 0x0000202F,
220 TSC_MULTIPLIER = 0x00002032,
221 TSC_MULTIPLIER_HIGH = 0x00002033,
222 GUEST_PHYSICAL_ADDRESS = 0x00002400,
223 GUEST_PHYSICAL_ADDRESS_HIGH = 0x00002401,
224 VMCS_LINK_POINTER = 0x00002800,
225 VMCS_LINK_POINTER_HIGH = 0x00002801,
226 GUEST_IA32_DEBUGCTL = 0x00002802,
227 GUEST_IA32_DEBUGCTL_HIGH = 0x00002803,
228 GUEST_IA32_PAT = 0x00002804,
229 GUEST_IA32_PAT_HIGH = 0x00002805,
230 GUEST_IA32_EFER = 0x00002806,
231 GUEST_IA32_EFER_HIGH = 0x00002807,
232 GUEST_IA32_PERF_GLOBAL_CTRL = 0x00002808,
233 GUEST_IA32_PERF_GLOBAL_CTRL_HIGH= 0x00002809,
234 GUEST_PDPTR0 = 0x0000280a,
235 GUEST_PDPTR0_HIGH = 0x0000280b,
236 GUEST_PDPTR1 = 0x0000280c,
237 GUEST_PDPTR1_HIGH = 0x0000280d,
238 GUEST_PDPTR2 = 0x0000280e,
239 GUEST_PDPTR2_HIGH = 0x0000280f,
240 GUEST_PDPTR3 = 0x00002810,
241 GUEST_PDPTR3_HIGH = 0x00002811,
242 GUEST_BNDCFGS = 0x00002812,
243 GUEST_BNDCFGS_HIGH = 0x00002813,
244 GUEST_IA32_RTIT_CTL = 0x00002814,
245 GUEST_IA32_RTIT_CTL_HIGH = 0x00002815,
246 HOST_IA32_PAT = 0x00002c00,
247 HOST_IA32_PAT_HIGH = 0x00002c01,
248 HOST_IA32_EFER = 0x00002c02,
249 HOST_IA32_EFER_HIGH = 0x00002c03,
250 HOST_IA32_PERF_GLOBAL_CTRL = 0x00002c04,
251 HOST_IA32_PERF_GLOBAL_CTRL_HIGH = 0x00002c05,
252 PIN_BASED_VM_EXEC_CONTROL = 0x00004000,
253 CPU_BASED_VM_EXEC_CONTROL = 0x00004002,
254 EXCEPTION_BITMAP = 0x00004004,
255 PAGE_FAULT_ERROR_CODE_MASK = 0x00004006,
256 PAGE_FAULT_ERROR_CODE_MATCH = 0x00004008,
257 CR3_TARGET_COUNT = 0x0000400a,
258 VM_EXIT_CONTROLS = 0x0000400c,
259 VM_EXIT_MSR_STORE_COUNT = 0x0000400e,
260 VM_EXIT_MSR_LOAD_COUNT = 0x00004010,
261 VM_ENTRY_CONTROLS = 0x00004012,
262 VM_ENTRY_MSR_LOAD_COUNT = 0x00004014,
263 VM_ENTRY_INTR_INFO_FIELD = 0x00004016,
264 VM_ENTRY_EXCEPTION_ERROR_CODE = 0x00004018,
265 VM_ENTRY_INSTRUCTION_LEN = 0x0000401a,
266 TPR_THRESHOLD = 0x0000401c,
267 SECONDARY_VM_EXEC_CONTROL = 0x0000401e,
268 PLE_GAP = 0x00004020,
269 PLE_WINDOW = 0x00004022,
270 VM_INSTRUCTION_ERROR = 0x00004400,
271 VM_EXIT_REASON = 0x00004402,
272 VM_EXIT_INTR_INFO = 0x00004404,
273 VM_EXIT_INTR_ERROR_CODE = 0x00004406,
274 IDT_VECTORING_INFO_FIELD = 0x00004408,
275 IDT_VECTORING_ERROR_CODE = 0x0000440a,
276 VM_EXIT_INSTRUCTION_LEN = 0x0000440c,
277 VMX_INSTRUCTION_INFO = 0x0000440e,
278 GUEST_ES_LIMIT = 0x00004800,
279 GUEST_CS_LIMIT = 0x00004802,
280 GUEST_SS_LIMIT = 0x00004804,
281 GUEST_DS_LIMIT = 0x00004806,
282 GUEST_FS_LIMIT = 0x00004808,
283 GUEST_GS_LIMIT = 0x0000480a,
284 GUEST_LDTR_LIMIT = 0x0000480c,
285 GUEST_TR_LIMIT = 0x0000480e,
286 GUEST_GDTR_LIMIT = 0x00004810,
287 GUEST_IDTR_LIMIT = 0x00004812,
288 GUEST_ES_AR_BYTES = 0x00004814,
289 GUEST_CS_AR_BYTES = 0x00004816,
290 GUEST_SS_AR_BYTES = 0x00004818,
291 GUEST_DS_AR_BYTES = 0x0000481a,
292 GUEST_FS_AR_BYTES = 0x0000481c,
293 GUEST_GS_AR_BYTES = 0x0000481e,
294 GUEST_LDTR_AR_BYTES = 0x00004820,
295 GUEST_TR_AR_BYTES = 0x00004822,
296 GUEST_INTERRUPTIBILITY_INFO = 0x00004824,
297 GUEST_ACTIVITY_STATE = 0X00004826,
298 GUEST_SYSENTER_CS = 0x0000482A,
299 VMX_PREEMPTION_TIMER_VALUE = 0x0000482E,
300 HOST_IA32_SYSENTER_CS = 0x00004c00,
301 CR0_GUEST_HOST_MASK = 0x00006000,
302 CR4_GUEST_HOST_MASK = 0x00006002,
303 CR0_READ_SHADOW = 0x00006004,
304 CR4_READ_SHADOW = 0x00006006,
305 CR3_TARGET_VALUE0 = 0x00006008,
306 CR3_TARGET_VALUE1 = 0x0000600a,
307 CR3_TARGET_VALUE2 = 0x0000600c,
308 CR3_TARGET_VALUE3 = 0x0000600e,
309 EXIT_QUALIFICATION = 0x00006400,
310 GUEST_LINEAR_ADDRESS = 0x0000640a,
311 GUEST_CR0 = 0x00006800,
312 GUEST_CR3 = 0x00006802,
313 GUEST_CR4 = 0x00006804,
314 GUEST_ES_BASE = 0x00006806,
315 GUEST_CS_BASE = 0x00006808,
316 GUEST_SS_BASE = 0x0000680a,
317 GUEST_DS_BASE = 0x0000680c,
318 GUEST_FS_BASE = 0x0000680e,
319 GUEST_GS_BASE = 0x00006810,
320 GUEST_LDTR_BASE = 0x00006812,
321 GUEST_TR_BASE = 0x00006814,
322 GUEST_GDTR_BASE = 0x00006816,
323 GUEST_IDTR_BASE = 0x00006818,
324 GUEST_DR7 = 0x0000681a,
325 GUEST_RSP = 0x0000681c,
326 GUEST_RIP = 0x0000681e,
327 GUEST_RFLAGS = 0x00006820,
328 GUEST_PENDING_DBG_EXCEPTIONS = 0x00006822,
329 GUEST_SYSENTER_ESP = 0x00006824,
330 GUEST_SYSENTER_EIP = 0x00006826,
331 HOST_CR0 = 0x00006c00,
332 HOST_CR3 = 0x00006c02,
333 HOST_CR4 = 0x00006c04,
334 HOST_FS_BASE = 0x00006c06,
335 HOST_GS_BASE = 0x00006c08,
336 HOST_TR_BASE = 0x00006c0a,
337 HOST_GDTR_BASE = 0x00006c0c,
338 HOST_IDTR_BASE = 0x00006c0e,
339 HOST_IA32_SYSENTER_ESP = 0x00006c10,
340 HOST_IA32_SYSENTER_EIP = 0x00006c12,
341 HOST_RSP = 0x00006c14,
342 HOST_RIP = 0x00006c16,
348 #define INTR_INFO_VECTOR_MASK 0xff /* 7:0 */
349 #define INTR_INFO_INTR_TYPE_MASK 0x700 /* 10:8 */
350 #define INTR_INFO_DELIVER_CODE_MASK 0x800 /* 11 */
351 #define INTR_INFO_UNBLOCK_NMI 0x1000 /* 12 */
352 #define INTR_INFO_VALID_MASK 0x80000000 /* 31 */
353 #define INTR_INFO_RESVD_BITS_MASK 0x7ffff000
360 #define INTR_TYPE_EXT_INTR (0 << 8) /* external interrupt */
370 #define GUEST_INTR_STATE_STI 0x00000001
371 #define GUEST_INTR_STATE_MOV_SS 0x00000002
372 #define GUEST_INTR_STATE_SMI 0x00000004
373 #define GUEST_INTR_STATE_NMI 0x00000008
376 #define GUEST_ACTIVITY_ACTIVE 0
384 #define CONTROL_REG_ACCESS_NUM 0x7 /* 2:0, number of control reg.*/
385 #define CONTROL_REG_ACCESS_TYPE 0x30 /* 5:4, access type */
386 #define CONTROL_REG_ACCESS_REG 0xf00 /* 10:8, general purpose reg. */
388 #define LMSW_SOURCE_DATA (0xFFFF << LMSW_SOURCE_DATA_SHIFT) /* 16:31 lmsw source */
389 #define REG_EAX (0 << 8)
409 #define DEBUG_REG_ACCESS_NUM 0x7 /* 2:0, number of debug reg. */
410 #define DEBUG_REG_ACCESS_TYPE 0x10 /* 4, direction of access */
411 #define TYPE_MOV_TO_DR (0 << 4)
413 #define DEBUG_REG_ACCESS_REG(eq) (((eq) >> 8) & 0xf) /* 11:8, general purpose reg. */
419 #define APIC_ACCESS_OFFSET 0xfff /* 11:0, offset within the APIC page */
420 #define APIC_ACCESS_TYPE 0xf000 /* 15:12, access type */
421 #define TYPE_LINEAR_APIC_INST_READ (0 << 12)
435 #define VMX_AR_TYPE_MASK 0x0f
450 #define VMX_AR_RESERVD_MASK 0xfffe0f00
452 #define TSS_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 0)
457 #define VMX_VPID_EXTENT_INDIVIDUAL_ADDR 0
478 #define VMX_VPID_INVVPID_BIT (1ull << 0) /* (32 - 32) */
485 #define VMX_EPTP_PWL_MASK 0x38ull
486 #define VMX_EPTP_PWL_4 0x18ull
487 #define VMX_EPTP_PWL_5 0x20ull
489 #define VMX_EPTP_MT_MASK 0x7ull
490 #define VMX_EPTP_MT_WB 0x6ull
491 #define VMX_EPTP_MT_UC 0x0ull
492 #define VMX_EPT_READABLE_MASK 0x1ull
493 #define VMX_EPT_WRITABLE_MASK 0x2ull
494 #define VMX_EPT_EXECUTABLE_MASK 0x4ull
519 #define VMX_EPT_IDENTITY_PAGETABLE_ADDR 0xfffbc000ul
531 ENTRY_FAIL_DEFAULT = 0,
540 #define EPT_VIOLATION_ACC_READ_BIT 0