1 /* SPDX-License-Identifier: GPL-2.0 */
120 	unsigned int full;  member
133 	unsigned int full;  member
144 	unsigned int full;  member
155 		/* Deep C-state Reset */
160 	unsigned int		full;  member
169 		/* Call-stack Mode Supported */
172 	unsigned int            full;  member
177 		/* Mispredict Bit Supported */
184 	unsigned int            full;  member
198  * Fixed-purpose performance events:
206  * All the fixed-mode PMCs are configured via this single MSR:
211  * There is no event-code assigned to the fixed-mode PMCs.
213  * For a fixed-mode PMC, which has an equivalent event on a general-purpose
214  * PMC, the event-code of the equivalent event is used for the fixed-mode PMC,
217  * For a fixed-mode PMC, which doesn't have an equivalent event, a
218  * pseudo-encoding is used, e.g., CPU_CLK_Unhalted.Ref and TOPDOWN.SLOTS.
219  * The pseudo event-code for a fixed-mode PMC must be 0x00.
220  * The pseudo umask-code is 0xX. The X equals the index of the fixed
221  * counter + 1, e.g., the fixed counter 2 has the pseudo-encoding 0x0300.
234 /* CPU_CLK_Unhalted.Ref: event=0x00,umask=0x3 (pseudo-encoding) */
239 /* TOPDOWN.SLOTS: event=0x00,umask=0x4 (pseudo-encoding) */
245  * We model BTS tracing as another fixed-mode PMC.
254  * The PERF_METRICS MSR is modeled as several magic fixed-mode PMCs, one for
269  * There is no event-code assigned to the TopDown events.
273  * For the metric events, the pseudo event-code is 0x00.
274  * The pseudo umask-code starts from the middle of the pseudo event
288 	return (unsigned)(idx - INTEL_PMC_IDX_METRIC_BASE) < INTEL_TD_METRIC_NUM;  in is_metric_idx()
296 #define INTEL_PMC_OTHER_TOPDOWN_BITS(bit)	\  argument
297 			(~(0x1ull << bit) & INTEL_PMC_MSK_TOPDOWN)
313  * We model guest LBR event tracing as another fixed-mode PMC like BTS.
315  * We choose bit 58 because it's used to indicate LBR stack frozen state
316  * for architectural perfmon v4, also we unconditionally mask that bit in
326  * Pseudo-encoding the guest LBR event as event=0x00,umask=0x1b,
327  * since it would claim bit 58 which is effectively Fixed26.
365  * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
366  * bit 0 is used to indicate the existence of IBS.
409 #define IBS_OP_MAX_CNT_EXT	0x007FFFFFULL	/* not a register bit mask */
427  * EXACT - the IP points to the exact instruction that triggered the
429  * VM    - original X86_VM_MASK; see set_linear_ip().
447  * We abuse bit 3 from flags to pass exact information, see perf_misc_flags
451 	(regs)->ip = (__ip);					\
452 	(regs)->sp = (unsigned long)__builtin_frame_address(0);	\
453 	(regs)->cs = __KERNEL_CS;				\
454 	regs->flags = 0;					\
493 	return -1;  in x86_perf_get_lbr()