Lines Matching defs:cpu_hw_events

224 struct cpu_hw_events {  struct
228 	struct perf_event	*events[X86_PMC_IDX_MAX]; /* in counter order */
229 	unsigned long		active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
230 	unsigned long		running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
231 	int			enabled;
233 	int			n_events; /* the # of events in the below arrays */
234 	int			n_added;  /* the # last events in the below arrays;
236 	int			n_txn;    /* the # last events in the below arrays;
238 	int			n_txn_pair;
239 	int			n_txn_metric;
240 	int			assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
241 	u64			tags[X86_PMC_IDX_MAX];
243 	struct perf_event	*event_list[X86_PMC_IDX_MAX]; /* in enabled order */
244 	struct event_constraint	*event_constraint[X86_PMC_IDX_MAX];
246 	int			n_excl; /* the number of exclusive events */
248 	unsigned int		txn_flags;
249 	int			is_fake;
254 	struct debug_store	*ds;
255 	void			*ds_pebs_vaddr;
256 	void			*ds_bts_vaddr;
257 	u64			pebs_enabled;
258 	int			n_pebs;
259 	int			n_large_pebs;
260 	int			n_pebs_via_pt;
261 	int			pebs_output;
264 	u64			pebs_data_cfg;
265 	u64			active_pebs_data_cfg;
266 	int			pebs_record_size;
271 	int				lbr_users;
272 	int				lbr_pebs_users;
273 	struct perf_branch_stack	lbr_stack;
274 	struct perf_branch_entry	lbr_entries[MAX_LBR_ENTRIES];
275 	union {
279 	u64				br_sel;
280 	void				*last_task_ctx;
281 	int				last_log_id;
282 	int				lbr_select;
283 	void				*lbr_xsave;
288 	u64				intel_ctrl_guest_mask;
289 	u64				intel_ctrl_host_mask;
290 	struct perf_guest_switch_msr	guest_switch_msrs[X86_PMC_IDX_MAX];
295 	u64				intel_cp_status;
301 	struct intel_shared_regs	*shared_regs;
305 	struct event_constraint *constraint_list; /* in enable order */
306 	struct intel_excl_cntrs		*excl_cntrs;
307 	int excl_thread_id; /* 0 or 1 */
312 	u64				tfa_shadow;
318 	int				n_metric;
323 	struct amd_nb			*amd_nb;
325 	u64				perf_ctr_virt_mask;
326 	int				n_pair; /* Large increment events */
328 	void				*kfree_on_online[X86_PERF_KFREE_MAX];