Lines Matching +full:top +full:- +full:level
1 // SPDX-License-Identifier: GPL-2.0
57 #define LEVEL(x) P(LVLNUM, x) macro
63 P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
64 OP_LH | P(LVL, L1) | LEVEL(L1) | P(SNOOP, NONE), /* 0x01: L1 local */
65 OP_LH | P(LVL, LFB) | LEVEL(LFB) | P(SNOOP, NONE), /* 0x02: LFB hit */
66 OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, NONE), /* 0x03: L2 hit */
67 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, NONE), /* 0x04: L3 hit */
68 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */
69 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */
70 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */
71 OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */
72 OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
73 OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | P(SNOOP, HIT), /* 0x0a: L3 miss, shared */
74 OP_LH | P(LVL, REM_RAM1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */
75 OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | SNOOP_NONE_MISS, /* 0x0c: L3 miss, excl */
76 OP_LH | P(LVL, REM_RAM1) | LEVEL(RAM) | REM | SNOOP_NONE_MISS, /* 0x0d: L3 miss, excl */
77 OP_LH | P(LVL, IO) | LEVEL(NA) | P(SNOOP, NONE), /* 0x0e: I/O */
78 OP_LH | P(LVL, UNC) | LEVEL(NA) | P(SNOOP, NONE), /* 0x0f: uncached */
84 pebs_data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT); in intel_pmu_pebs_data_source_nhm()
85 pebs_data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); in intel_pmu_pebs_data_source_nhm()
86 pebs_data_source[0x07] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); in intel_pmu_pebs_data_source_nhm()
91 u64 pmem_or_l4 = pmem ? LEVEL(PMEM) : LEVEL(L4); in intel_pmu_pebs_data_source_skl()
95 pebs_data_source[0x0b] = OP_LH | LEVEL(RAM) | REM | P(SNOOP, NONE); in intel_pmu_pebs_data_source_skl()
96 pebs_data_source[0x0c] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOPX, FWD); in intel_pmu_pebs_data_source_skl()
97 pebs_data_source[0x0d] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOP, HITM); in intel_pmu_pebs_data_source_skl()
109 * 1 = stored missed 2nd level TLB in precise_store_data()
112 * otherwise hit 2nd level TLB in precise_store_data()
144 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) in precise_datala_hsw()
146 else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW) in precise_datala_hsw()
157 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) { in precise_datala_hsw()
174 * use the mapping table for bit 0-3 in load_latency_data()
187 * 0 = did not miss 2nd level TLB in load_latency_data()
188 * 1 = missed 2nd level TLB in load_latency_data()
299 * This is a cross-CPU update of the cpu_entry_area, we must shoot down in ds_update_cea()
338 struct debug_store *ds = hwev->ds; in alloc_pebs_buffer()
348 return -ENOMEM; in alloc_pebs_buffer()
358 return -ENOMEM; in alloc_pebs_buffer()
362 hwev->ds_pebs_vaddr = buffer; in alloc_pebs_buffer()
364 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer; in alloc_pebs_buffer()
365 ds->pebs_buffer_base = (unsigned long) cea; in alloc_pebs_buffer()
367 ds->pebs_index = ds->pebs_buffer_base; in alloc_pebs_buffer()
369 ds->pebs_absolute_maximum = ds->pebs_buffer_base + max; in alloc_pebs_buffer()
385 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer; in release_pebs_buffer()
387 dsfree_pages(hwev->ds_pebs_vaddr, x86_pmu.pebs_buffer_size); in release_pebs_buffer()
388 hwev->ds_pebs_vaddr = NULL; in release_pebs_buffer()
394 struct debug_store *ds = hwev->ds; in alloc_bts_buffer()
404 return -ENOMEM; in alloc_bts_buffer()
406 hwev->ds_bts_vaddr = buffer; in alloc_bts_buffer()
408 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.bts_buffer; in alloc_bts_buffer()
409 ds->bts_buffer_base = (unsigned long) cea; in alloc_bts_buffer()
411 ds->bts_index = ds->bts_buffer_base; in alloc_bts_buffer()
413 ds->bts_absolute_maximum = ds->bts_buffer_base + in alloc_bts_buffer()
415 ds->bts_interrupt_threshold = ds->bts_absolute_maximum - in alloc_bts_buffer()
429 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.bts_buffer; in release_bts_buffer()
431 dsfree_pages(hwev->ds_bts_vaddr, BTS_BUFFER_SIZE); in release_bts_buffer()
432 hwev->ds_bts_vaddr = NULL; in release_bts_buffer()
437 struct debug_store *ds = &get_cpu_entry_area(cpu)->cpu_debug_store; in alloc_ds_buffer()
569 if (!cpuc->ds) in intel_pmu_disable_bts()
584 struct debug_store *ds = cpuc->ds; in intel_pmu_drain_bts_buffer()
590 struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; in intel_pmu_drain_bts_buffer()
591 struct bts_record *at, *base, *top; in intel_pmu_drain_bts_buffer() local
604 base = (struct bts_record *)(unsigned long)ds->bts_buffer_base; in intel_pmu_drain_bts_buffer()
605 top = (struct bts_record *)(unsigned long)ds->bts_index; in intel_pmu_drain_bts_buffer()
607 if (top <= base) in intel_pmu_drain_bts_buffer()
612 ds->bts_index = ds->bts_buffer_base; in intel_pmu_drain_bts_buffer()
614 perf_sample_data_init(&data, 0, event->hw.last_period); in intel_pmu_drain_bts_buffer()
626 for (at = base; at < top; at++) { in intel_pmu_drain_bts_buffer()
632 if (event->attr.exclude_kernel && in intel_pmu_drain_bts_buffer()
633 (kernel_ip(at->from) || kernel_ip(at->to))) in intel_pmu_drain_bts_buffer()
646 header.size * (top - base - skip))) in intel_pmu_drain_bts_buffer()
649 for (at = base; at < top; at++) { in intel_pmu_drain_bts_buffer()
651 if (event->attr.exclude_kernel && in intel_pmu_drain_bts_buffer()
652 (kernel_ip(at->from) || kernel_ip(at->to))) in intel_pmu_drain_bts_buffer()
655 data.ip = at->from; in intel_pmu_drain_bts_buffer()
656 data.addr = at->to; in intel_pmu_drain_bts_buffer()
664 event->hw.interrupts++; in intel_pmu_drain_bts_buffer()
665 event->pending_kill = POLL_IN; in intel_pmu_drain_bts_buffer()
877 if (!event->attr.precise_ip) in intel_pebs_constraints()
882 if (constraint_match(c, event->hw.config)) { in intel_pebs_constraints()
883 event->hw.flags |= c->flags; in intel_pebs_constraints()
900 * We need the sched_task callback even for per-cpu events when we use
906 if (cpuc->n_pebs == cpuc->n_pebs_via_pt) in pebs_needs_sched_cb()
909 return cpuc->n_pebs && (cpuc->n_pebs == cpuc->n_large_pebs); in pebs_needs_sched_cb()
922 struct debug_store *ds = cpuc->ds; in pebs_update_threshold()
926 if (cpuc->n_pebs_via_pt) in pebs_update_threshold()
934 if (cpuc->n_pebs == cpuc->n_large_pebs) { in pebs_update_threshold()
935 threshold = ds->pebs_absolute_maximum - in pebs_update_threshold()
936 reserved * cpuc->pebs_record_size; in pebs_update_threshold()
938 threshold = ds->pebs_buffer_base + cpuc->pebs_record_size; in pebs_update_threshold()
941 ds->pebs_interrupt_threshold = threshold; in pebs_update_threshold()
947 u64 pebs_data_cfg = cpuc->pebs_data_cfg; in adaptive_pebs_record_size_update()
959 cpuc->pebs_record_size = sz; in adaptive_pebs_record_size_update()
968 struct perf_event_attr *attr = &event->attr; in pebs_update_adaptive_cfg()
969 u64 sample_type = attr->sample_type; in pebs_update_adaptive_cfg()
974 attr->precise_ip > 1) in pebs_update_adaptive_cfg()
987 (attr->sample_regs_intr & PEBS_GP_REGS); in pebs_update_adaptive_cfg()
990 ((attr->config & INTEL_ARCH_EVENT_MASK) == in pebs_update_adaptive_cfg()
993 if (gprs || (attr->precise_ip < 2) || tsx_weight) in pebs_update_adaptive_cfg()
997 (attr->sample_regs_intr & PERF_REG_EXTENDED_MASK)) in pebs_update_adaptive_cfg()
1006 ((x86_pmu.lbr_nr-1) << PEBS_DATACFG_LBR_SHIFT); in pebs_update_adaptive_cfg()
1016 struct pmu *pmu = event->ctx->pmu; in pebs_update_state()
1022 bool update = cpuc->n_pebs == 1; in pebs_update_state()
1041 if (cpuc->n_pebs == 1) { in pebs_update_state()
1042 cpuc->pebs_data_cfg = 0; in pebs_update_state()
1043 cpuc->pebs_record_size = sizeof(struct pebs_basic); in pebs_update_state()
1049 if (pebs_data_cfg & ~cpuc->pebs_data_cfg) { in pebs_update_state()
1050 cpuc->pebs_data_cfg |= pebs_data_cfg; in pebs_update_state()
1063 struct hw_perf_event *hwc = &event->hw; in intel_pmu_pebs_add()
1066 cpuc->n_pebs++; in intel_pmu_pebs_add()
1067 if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS) in intel_pmu_pebs_add()
1068 cpuc->n_large_pebs++; in intel_pmu_pebs_add()
1069 if (hwc->flags & PERF_X86_EVENT_PEBS_VIA_PT) in intel_pmu_pebs_add()
1070 cpuc->n_pebs_via_pt++; in intel_pmu_pebs_add()
1082 if (!(cpuc->pebs_enabled & ~PEBS_VIA_PT_MASK)) in intel_pmu_pebs_via_pt_disable()
1083 cpuc->pebs_enabled &= ~PEBS_VIA_PT_MASK; in intel_pmu_pebs_via_pt_disable()
1089 struct hw_perf_event *hwc = &event->hw; in intel_pmu_pebs_via_pt_enable()
1090 struct debug_store *ds = cpuc->ds; in intel_pmu_pebs_via_pt_enable()
1095 if (!(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS)) in intel_pmu_pebs_via_pt_enable()
1096 cpuc->pebs_enabled |= PEBS_PMI_AFTER_EACH_RECORD; in intel_pmu_pebs_via_pt_enable()
1098 cpuc->pebs_enabled |= PEBS_OUTPUT_PT; in intel_pmu_pebs_via_pt_enable()
1100 wrmsrl(MSR_RELOAD_PMC0 + hwc->idx, ds->pebs_event_reset[hwc->idx]); in intel_pmu_pebs_via_pt_enable()
1106 struct hw_perf_event *hwc = &event->hw; in intel_pmu_pebs_enable()
1107 struct debug_store *ds = cpuc->ds; in intel_pmu_pebs_enable()
1109 hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT; in intel_pmu_pebs_enable()
1111 cpuc->pebs_enabled |= 1ULL << hwc->idx; in intel_pmu_pebs_enable()
1113 if ((event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) && (x86_pmu.version < 5)) in intel_pmu_pebs_enable()
1114 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32); in intel_pmu_pebs_enable()
1115 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST) in intel_pmu_pebs_enable()
1116 cpuc->pebs_enabled |= 1ULL << 63; in intel_pmu_pebs_enable()
1119 hwc->config |= ICL_EVENTSEL_ADAPTIVE; in intel_pmu_pebs_enable()
1120 if (cpuc->pebs_data_cfg != cpuc->active_pebs_data_cfg) { in intel_pmu_pebs_enable()
1121 wrmsrl(MSR_PEBS_DATA_CFG, cpuc->pebs_data_cfg); in intel_pmu_pebs_enable()
1122 cpuc->active_pebs_data_cfg = cpuc->pebs_data_cfg; in intel_pmu_pebs_enable()
1127 * Use auto-reload if possible to save a MSR write in the PMI. in intel_pmu_pebs_enable()
1130 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) { in intel_pmu_pebs_enable()
1131 unsigned int idx = hwc->idx; in intel_pmu_pebs_enable()
1134 idx = MAX_PEBS_EVENTS + (idx - INTEL_PMC_IDX_FIXED); in intel_pmu_pebs_enable()
1135 ds->pebs_event_reset[idx] = in intel_pmu_pebs_enable()
1136 (u64)(-hwc->sample_period) & x86_pmu.cntval_mask; in intel_pmu_pebs_enable()
1138 ds->pebs_event_reset[hwc->idx] = 0; in intel_pmu_pebs_enable()
1147 struct hw_perf_event *hwc = &event->hw; in intel_pmu_pebs_del()
1150 cpuc->n_pebs--; in intel_pmu_pebs_del()
1151 if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS) in intel_pmu_pebs_del()
1152 cpuc->n_large_pebs--; in intel_pmu_pebs_del()
1153 if (hwc->flags & PERF_X86_EVENT_PEBS_VIA_PT) in intel_pmu_pebs_del()
1154 cpuc->n_pebs_via_pt--; in intel_pmu_pebs_del()
1162 struct hw_perf_event *hwc = &event->hw; in intel_pmu_pebs_disable()
1164 if (cpuc->n_pebs == cpuc->n_large_pebs && in intel_pmu_pebs_disable()
1165 cpuc->n_pebs != cpuc->n_pebs_via_pt) in intel_pmu_pebs_disable()
1168 cpuc->pebs_enabled &= ~(1ULL << hwc->idx); in intel_pmu_pebs_disable()
1170 if ((event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) && in intel_pmu_pebs_disable()
1172 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32)); in intel_pmu_pebs_disable()
1173 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST) in intel_pmu_pebs_disable()
1174 cpuc->pebs_enabled &= ~(1ULL << 63); in intel_pmu_pebs_disable()
1178 if (cpuc->enabled) in intel_pmu_pebs_disable()
1179 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); in intel_pmu_pebs_disable()
1181 hwc->config |= ARCH_PERFMON_EVENTSEL_INT; in intel_pmu_pebs_disable()
1188 if (cpuc->pebs_enabled) in intel_pmu_pebs_enable_all()
1189 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); in intel_pmu_pebs_enable_all()
1196 if (cpuc->pebs_enabled) in intel_pmu_pebs_disable_all()
1203 unsigned long from = cpuc->lbr_entries[0].from; in intel_pmu_pebs_fixup_ip()
1204 unsigned long old_to, to = cpuc->lbr_entries[0].to; in intel_pmu_pebs_fixup_ip()
1205 unsigned long ip = regs->ip; in intel_pmu_pebs_fixup_ip()
1219 if (!cpuc->lbr_stack.nr || !from || !to) in intel_pmu_pebs_fixup_ip()
1232 if ((ip - to) > PEBS_FIXUP_SIZE) in intel_pmu_pebs_fixup_ip()
1243 size = ip - to; in intel_pmu_pebs_fixup_ip()
1279 size -= insn.length; in intel_pmu_pebs_fixup_ip()
1316 return ((struct pebs_record_nhm *)n)->status; in get_pebs_status()
1317 return ((struct pebs_basic *)n)->applicable_counters; in get_pebs_status()
1328 int fl = event->hw.flags; in get_data_src()
1357 sample_type = event->attr.sample_type; in setup_pebs_fixed_sample_data()
1358 fll = event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT; in setup_pebs_fixed_sample_data()
1360 perf_sample_data_init(data, 0, event->hw.last_period); in setup_pebs_fixed_sample_data()
1362 data->period = event->hw.last_period; in setup_pebs_fixed_sample_data()
1365 * Use latency for weight (only avail with PEBS-LL) in setup_pebs_fixed_sample_data()
1368 data->weight = pebs->lat; in setup_pebs_fixed_sample_data()
1374 data->data_src.val = get_data_src(event, pebs->dse); in setup_pebs_fixed_sample_data()
1383 data->callchain = perf_callchain(event, iregs); in setup_pebs_fixed_sample_data()
1399 regs->flags = pebs->flags & ~PERF_EFLAGS_EXACT; in setup_pebs_fixed_sample_data()
1402 regs->ax = pebs->ax; in setup_pebs_fixed_sample_data()
1403 regs->bx = pebs->bx; in setup_pebs_fixed_sample_data()
1404 regs->cx = pebs->cx; in setup_pebs_fixed_sample_data()
1405 regs->dx = pebs->dx; in setup_pebs_fixed_sample_data()
1406 regs->si = pebs->si; in setup_pebs_fixed_sample_data()
1407 regs->di = pebs->di; in setup_pebs_fixed_sample_data()
1409 regs->bp = pebs->bp; in setup_pebs_fixed_sample_data()
1410 regs->sp = pebs->sp; in setup_pebs_fixed_sample_data()
1413 regs->r8 = pebs->r8; in setup_pebs_fixed_sample_data()
1414 regs->r9 = pebs->r9; in setup_pebs_fixed_sample_data()
1415 regs->r10 = pebs->r10; in setup_pebs_fixed_sample_data()
1416 regs->r11 = pebs->r11; in setup_pebs_fixed_sample_data()
1417 regs->r12 = pebs->r12; in setup_pebs_fixed_sample_data()
1418 regs->r13 = pebs->r13; in setup_pebs_fixed_sample_data()
1419 regs->r14 = pebs->r14; in setup_pebs_fixed_sample_data()
1420 regs->r15 = pebs->r15; in setup_pebs_fixed_sample_data()
1424 if (event->attr.precise_ip > 1) { in setup_pebs_fixed_sample_data()
1427 * (real IP) which fixes the off-by-1 skid in hardware. in setup_pebs_fixed_sample_data()
1431 set_linear_ip(regs, pebs->real_ip); in setup_pebs_fixed_sample_data()
1432 regs->flags |= PERF_EFLAGS_EXACT; in setup_pebs_fixed_sample_data()
1434 /* Otherwise, use PEBS off-by-1 IP: */ in setup_pebs_fixed_sample_data()
1435 set_linear_ip(regs, pebs->ip); in setup_pebs_fixed_sample_data()
1438 * With precise_ip >= 2, try to fix up the off-by-1 IP in setup_pebs_fixed_sample_data()
1440 * corrects regs->ip and calls set_linear_ip() on regs: in setup_pebs_fixed_sample_data()
1443 regs->flags |= PERF_EFLAGS_EXACT; in setup_pebs_fixed_sample_data()
1447 * When precise_ip == 1, return the PEBS off-by-1 IP, in setup_pebs_fixed_sample_data()
1450 set_linear_ip(regs, pebs->ip); in setup_pebs_fixed_sample_data()
1456 data->addr = pebs->dla; in setup_pebs_fixed_sample_data()
1461 data->weight = intel_get_tsx_weight(pebs->tsx_tuning); in setup_pebs_fixed_sample_data()
1464 data->txn = intel_get_tsx_transaction(pebs->tsx_tuning, in setup_pebs_fixed_sample_data()
1465 pebs->ax); in setup_pebs_fixed_sample_data()
1475 event->attr.use_clockid == 0) in setup_pebs_fixed_sample_data()
1476 data->time = native_sched_clock_from_tsc(pebs->tsc); in setup_pebs_fixed_sample_data()
1479 data->br_stack = &cpuc->lbr_stack; in setup_pebs_fixed_sample_data()
1485 regs->ax = gprs->ax; in adaptive_pebs_save_regs()
1486 regs->bx = gprs->bx; in adaptive_pebs_save_regs()
1487 regs->cx = gprs->cx; in adaptive_pebs_save_regs()
1488 regs->dx = gprs->dx; in adaptive_pebs_save_regs()
1489 regs->si = gprs->si; in adaptive_pebs_save_regs()
1490 regs->di = gprs->di; in adaptive_pebs_save_regs()
1491 regs->bp = gprs->bp; in adaptive_pebs_save_regs()
1492 regs->sp = gprs->sp; in adaptive_pebs_save_regs()
1494 regs->r8 = gprs->r8; in adaptive_pebs_save_regs()
1495 regs->r9 = gprs->r9; in adaptive_pebs_save_regs()
1496 regs->r10 = gprs->r10; in adaptive_pebs_save_regs()
1497 regs->r11 = gprs->r11; in adaptive_pebs_save_regs()
1498 regs->r12 = gprs->r12; in adaptive_pebs_save_regs()
1499 regs->r13 = gprs->r13; in adaptive_pebs_save_regs()
1500 regs->r14 = gprs->r14; in adaptive_pebs_save_regs()
1501 regs->r15 = gprs->r15; in adaptive_pebs_save_regs()
1527 perf_regs->xmm_regs = NULL; in setup_pebs_adaptive_sample_data()
1529 sample_type = event->attr.sample_type; in setup_pebs_adaptive_sample_data()
1530 format_size = basic->format_size; in setup_pebs_adaptive_sample_data()
1531 perf_sample_data_init(data, 0, event->hw.last_period); in setup_pebs_adaptive_sample_data()
1532 data->period = event->hw.last_period; in setup_pebs_adaptive_sample_data()
1534 if (event->attr.use_clockid == 0) in setup_pebs_adaptive_sample_data()
1535 data->time = native_sched_clock_from_tsc(basic->tsc); in setup_pebs_adaptive_sample_data()
1544 data->callchain = perf_callchain(event, iregs); in setup_pebs_adaptive_sample_data()
1548 set_linear_ip(regs, basic->ip); in setup_pebs_adaptive_sample_data()
1549 regs->flags = PERF_EFLAGS_EXACT; in setup_pebs_adaptive_sample_data()
1553 * But PERF_SAMPLE_TRANSACTION needs gprs->ax. in setup_pebs_adaptive_sample_data()
1565 if (event->attr.precise_ip < 2) { in setup_pebs_adaptive_sample_data()
1566 set_linear_ip(regs, gprs->ip); in setup_pebs_adaptive_sample_data()
1567 regs->flags &= ~PERF_EFLAGS_EXACT; in setup_pebs_adaptive_sample_data()
1576 data->weight = meminfo->latency ?: in setup_pebs_adaptive_sample_data()
1577 intel_get_tsx_weight(meminfo->tsx_tuning); in setup_pebs_adaptive_sample_data()
1580 data->data_src.val = get_data_src(event, meminfo->aux); in setup_pebs_adaptive_sample_data()
1583 data->addr = meminfo->address; in setup_pebs_adaptive_sample_data()
1586 data->txn = intel_get_tsx_transaction(meminfo->tsx_tuning, in setup_pebs_adaptive_sample_data()
1587 gprs ? gprs->ax : 0); in setup_pebs_adaptive_sample_data()
1594 perf_regs->xmm_regs = xmm->xmm; in setup_pebs_adaptive_sample_data()
1605 data->br_stack = &cpuc->lbr_stack; in setup_pebs_adaptive_sample_data()
1612 (u64)(next_record - __pebs), in setup_pebs_adaptive_sample_data()
1613 basic->format_size); in setup_pebs_adaptive_sample_data()
1617 get_next_pebs_record_by_bit(void *base, void *top, int bit) in get_next_pebs_record_by_bit() argument
1633 for (at = base; at < top; at += cpuc->pebs_record_size) { in get_next_pebs_record_by_bit()
1644 /* clear non-PEBS bit and re-check */ in get_next_pebs_record_by_bit()
1645 pebs_status = status & cpuc->pebs_enabled; in get_next_pebs_record_by_bit()
1656 WARN_ON(!(event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)); in intel_pmu_auto_reload_read()
1658 perf_pmu_disable(event->pmu); in intel_pmu_auto_reload_read()
1660 perf_pmu_enable(event->pmu); in intel_pmu_auto_reload_read()
1664 * Special variant of intel_pmu_save_and_restart() for auto-reload.
1669 struct hw_perf_event *hwc = &event->hw; in intel_pmu_save_and_restart_reload()
1670 int shift = 64 - x86_pmu.cntval_bits; in intel_pmu_save_and_restart_reload()
1671 u64 period = hwc->sample_period; in intel_pmu_save_and_restart_reload()
1682 prev_raw_count = local64_read(&hwc->prev_count); in intel_pmu_save_and_restart_reload()
1683 rdpmcl(hwc->event_base_rdpmc, new_raw_count); in intel_pmu_save_and_restart_reload()
1684 local64_set(&hwc->prev_count, new_raw_count); in intel_pmu_save_and_restart_reload()
1690 * [-period, 0] in intel_pmu_save_and_restart_reload()
1694 * A) value2 - value1; in intel_pmu_save_and_restart_reload()
1697 * B) (0 - value1) + (value2 - (-period)); in intel_pmu_save_and_restart_reload()
1700 * C) (0 - value1) + (n - 1) * (period) + (value2 - (-period)); in intel_pmu_save_and_restart_reload()
1704 * discrete interval, where the first term is to the top of the in intel_pmu_save_and_restart_reload()
1711 * value2 - value1 + n * period in intel_pmu_save_and_restart_reload()
1715 local64_add(new - old + count * period, &event->count); in intel_pmu_save_and_restart_reload()
1717 local64_set(&hwc->period_left, -new); in intel_pmu_save_and_restart_reload()
1728 void *base, void *top, in __intel_pmu_pebs_event() argument
1737 struct hw_perf_event *hwc = &event->hw; in __intel_pmu_pebs_event()
1740 void *at = get_next_pebs_record_by_bit(base, top, bit); in __intel_pmu_pebs_event()
1743 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) { in __intel_pmu_pebs_event()
1745 * Now, auto-reload is only enabled in fixed period mode. in __intel_pmu_pebs_event()
1746 * The reload value is always hwc->sample_period. in __intel_pmu_pebs_event()
1747 * May need to change it, if auto-reload is enabled in in __intel_pmu_pebs_event()
1760 at += cpuc->pebs_record_size; in __intel_pmu_pebs_event()
1761 at = get_next_pebs_record_by_bit(at, top, bit); in __intel_pmu_pebs_event()
1762 count--; in __intel_pmu_pebs_event()
1768 * The PEBS records may be drained in the non-overflow context, in __intel_pmu_pebs_event()
1787 struct debug_store *ds = cpuc->ds; in intel_pmu_drain_pebs_core()
1788 struct perf_event *event = cpuc->events[0]; /* PMC0 only */ in intel_pmu_drain_pebs_core()
1789 struct pebs_record_core *at, *top; in intel_pmu_drain_pebs_core() local
1795 at = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base; in intel_pmu_drain_pebs_core()
1796 top = (struct pebs_record_core *)(unsigned long)ds->pebs_index; in intel_pmu_drain_pebs_core()
1801 ds->pebs_index = ds->pebs_buffer_base; in intel_pmu_drain_pebs_core()
1803 if (!test_bit(0, cpuc->active_mask)) in intel_pmu_drain_pebs_core()
1808 if (!event->attr.precise_ip) in intel_pmu_drain_pebs_core()
1811 n = top - at; in intel_pmu_drain_pebs_core()
1813 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD) in intel_pmu_drain_pebs_core()
1818 __intel_pmu_pebs_event(event, iregs, data, at, top, 0, n, in intel_pmu_drain_pebs_core()
1829 * for auto-reload event in pmu::read(). There are no in intel_pmu_pebs_event_update_no_drain()
1832 * update the event->count for this case. in intel_pmu_pebs_event_update_no_drain()
1834 for_each_set_bit(bit, (unsigned long *)&cpuc->pebs_enabled, size) { in intel_pmu_pebs_event_update_no_drain()
1835 event = cpuc->events[bit]; in intel_pmu_pebs_event_update_no_drain()
1836 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD) in intel_pmu_pebs_event_update_no_drain()
1844 struct debug_store *ds = cpuc->ds; in intel_pmu_drain_pebs_nhm()
1846 void *base, *at, *top; in intel_pmu_drain_pebs_nhm() local
1855 base = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base; in intel_pmu_drain_pebs_nhm()
1856 top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index; in intel_pmu_drain_pebs_nhm()
1858 ds->pebs_index = ds->pebs_buffer_base; in intel_pmu_drain_pebs_nhm()
1860 mask = (1ULL << x86_pmu.max_pebs_events) - 1; in intel_pmu_drain_pebs_nhm()
1863 mask |= ((1ULL << x86_pmu.num_counters_fixed) - 1) << INTEL_PMC_IDX_FIXED; in intel_pmu_drain_pebs_nhm()
1867 if (unlikely(base >= top)) { in intel_pmu_drain_pebs_nhm()
1872 for (at = base; at < top; at += x86_pmu.pebs_record_size) { in intel_pmu_drain_pebs_nhm()
1876 pebs_status = p->status & cpuc->pebs_enabled; in intel_pmu_drain_pebs_nhm()
1895 if (!pebs_status && cpuc->pebs_enabled && in intel_pmu_drain_pebs_nhm()
1896 !(cpuc->pebs_enabled & (cpuc->pebs_enabled-1))) in intel_pmu_drain_pebs_nhm()
1897 pebs_status = cpuc->pebs_enabled; in intel_pmu_drain_pebs_nhm()
1909 * If these events include one PEBS and multiple non-PEBS in intel_pmu_drain_pebs_nhm()
1932 event = cpuc->events[bit]; in intel_pmu_drain_pebs_nhm()
1936 if (WARN_ON_ONCE(!event->attr.precise_ip)) in intel_pmu_drain_pebs_nhm()
1949 top, bit, counts[bit], in intel_pmu_drain_pebs_nhm()
1959 struct debug_store *ds = cpuc->ds; in intel_pmu_drain_pebs_icl()
1961 void *base, *at, *top; in intel_pmu_drain_pebs_icl() local
1968 base = (struct pebs_basic *)(unsigned long)ds->pebs_buffer_base; in intel_pmu_drain_pebs_icl()
1969 top = (struct pebs_basic *)(unsigned long)ds->pebs_index; in intel_pmu_drain_pebs_icl()
1971 ds->pebs_index = ds->pebs_buffer_base; in intel_pmu_drain_pebs_icl()
1973 mask = ((1ULL << x86_pmu.max_pebs_events) - 1) | in intel_pmu_drain_pebs_icl()
1974 (((1ULL << x86_pmu.num_counters_fixed) - 1) << INTEL_PMC_IDX_FIXED); in intel_pmu_drain_pebs_icl()
1977 if (unlikely(base >= top)) { in intel_pmu_drain_pebs_icl()
1982 for (at = base; at < top; at += cpuc->pebs_record_size) { in intel_pmu_drain_pebs_icl()
1985 pebs_status = get_pebs_status(at) & cpuc->pebs_enabled; in intel_pmu_drain_pebs_icl()
1996 event = cpuc->events[bit]; in intel_pmu_drain_pebs_icl()
2000 if (WARN_ON_ONCE(!event->attr.precise_ip)) in intel_pmu_drain_pebs_icl()
2004 top, bit, counts[bit], in intel_pmu_drain_pebs_icl()
2028 char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-'; in intel_ds_init()
2078 pebs_qual = "-baseline"; in intel_ds_init()
2079 x86_get_pmu()->capabilities |= PERF_PMU_CAP_EXTENDED_REGS; in intel_ds_init()
2093 pr_cont("PEBS-via-PT, "); in intel_ds_init()
2094 x86_get_pmu()->capabilities |= PERF_PMU_CAP_AUX_OUTPUT; in intel_ds_init()