Lines Matching +full:1 +full:c
56 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
74 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
98 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
110 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
137 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
179 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
187 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
194 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
247 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
251 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
302 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */
311 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */
312 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */
341 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
367 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
396 #define SKL_DEMAND_RFO BIT_ULL(1)
435 [ C(L1D ) ] = {
436 [ C(OP_READ) ] = {
437 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
438 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
440 [ C(OP_WRITE) ] = {
441 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
442 [ C(RESULT_MISS) ] = 0x0,
444 [ C(OP_PREFETCH) ] = {
445 [ C(RESULT_ACCESS) ] = 0x0,
446 [ C(RESULT_MISS) ] = 0x0,
449 [ C(L1I ) ] = {
450 [ C(OP_READ) ] = {
451 [ C(RESULT_ACCESS) ] = 0x0,
452 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */
454 [ C(OP_WRITE) ] = {
455 [ C(RESULT_ACCESS) ] = -1,
456 [ C(RESULT_MISS) ] = -1,
458 [ C(OP_PREFETCH) ] = {
459 [ C(RESULT_ACCESS) ] = 0x0,
460 [ C(RESULT_MISS) ] = 0x0,
463 [ C(LL ) ] = {
464 [ C(OP_READ) ] = {
465 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
466 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
468 [ C(OP_WRITE) ] = {
469 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
470 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
472 [ C(OP_PREFETCH) ] = {
473 [ C(RESULT_ACCESS) ] = 0x0,
474 [ C(RESULT_MISS) ] = 0x0,
477 [ C(DTLB) ] = {
478 [ C(OP_READ) ] = {
479 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
480 [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
482 [ C(OP_WRITE) ] = {
483 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
484 [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
486 [ C(OP_PREFETCH) ] = {
487 [ C(RESULT_ACCESS) ] = 0x0,
488 [ C(RESULT_MISS) ] = 0x0,
491 [ C(ITLB) ] = {
492 [ C(OP_READ) ] = {
493 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */
494 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */
496 [ C(OP_WRITE) ] = {
497 [ C(RESULT_ACCESS) ] = -1,
498 [ C(RESULT_MISS) ] = -1,
500 [ C(OP_PREFETCH) ] = {
501 [ C(RESULT_ACCESS) ] = -1,
502 [ C(RESULT_MISS) ] = -1,
505 [ C(BPU ) ] = {
506 [ C(OP_READ) ] = {
507 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
508 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
510 [ C(OP_WRITE) ] = {
511 [ C(RESULT_ACCESS) ] = -1,
512 [ C(RESULT_MISS) ] = -1,
514 [ C(OP_PREFETCH) ] = {
515 [ C(RESULT_ACCESS) ] = -1,
516 [ C(RESULT_MISS) ] = -1,
519 [ C(NODE) ] = {
520 [ C(OP_READ) ] = {
521 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
522 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
524 [ C(OP_WRITE) ] = {
525 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
526 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
528 [ C(OP_PREFETCH) ] = {
529 [ C(RESULT_ACCESS) ] = 0x0,
530 [ C(RESULT_MISS) ] = 0x0,
540 [ C(LL ) ] = {
541 [ C(OP_READ) ] = {
542 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
544 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
548 [ C(OP_WRITE) ] = {
549 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
551 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
555 [ C(OP_PREFETCH) ] = {
556 [ C(RESULT_ACCESS) ] = 0x0,
557 [ C(RESULT_MISS) ] = 0x0,
560 [ C(NODE) ] = {
561 [ C(OP_READ) ] = {
562 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
564 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
567 [ C(OP_WRITE) ] = {
568 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
570 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
573 [ C(OP_PREFETCH) ] = {
574 [ C(RESULT_ACCESS) ] = 0x0,
575 [ C(RESULT_MISS) ] = 0x0,
580 #define SNB_DMND_DATA_RD (1ULL << 0)
581 #define SNB_DMND_RFO (1ULL << 1)
582 #define SNB_DMND_IFETCH (1ULL << 2)
583 #define SNB_DMND_WB (1ULL << 3)
584 #define SNB_PF_DATA_RD (1ULL << 4)
585 #define SNB_PF_RFO (1ULL << 5)
586 #define SNB_PF_IFETCH (1ULL << 6)
587 #define SNB_LLC_DATA_RD (1ULL << 7)
588 #define SNB_LLC_RFO (1ULL << 8)
589 #define SNB_LLC_IFETCH (1ULL << 9)
590 #define SNB_BUS_LOCKS (1ULL << 10)
591 #define SNB_STRM_ST (1ULL << 11)
592 #define SNB_OTHER (1ULL << 15)
593 #define SNB_RESP_ANY (1ULL << 16)
594 #define SNB_NO_SUPP (1ULL << 17)
595 #define SNB_LLC_HITM (1ULL << 18)
596 #define SNB_LLC_HITE (1ULL << 19)
597 #define SNB_LLC_HITS (1ULL << 20)
598 #define SNB_LLC_HITF (1ULL << 21)
599 #define SNB_LOCAL (1ULL << 22)
601 #define SNB_SNP_NONE (1ULL << 31)
602 #define SNB_SNP_NOT_NEEDED (1ULL << 32)
603 #define SNB_SNP_MISS (1ULL << 33)
604 #define SNB_NO_FWD (1ULL << 34)
605 #define SNB_SNP_FWD (1ULL << 35)
606 #define SNB_HITM (1ULL << 36)
607 #define SNB_NON_DRAM (1ULL << 37)
628 [ C(LL ) ] = {
629 [ C(OP_READ) ] = {
630 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
631 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
633 [ C(OP_WRITE) ] = {
634 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
635 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
637 [ C(OP_PREFETCH) ] = {
638 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
639 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
642 [ C(NODE) ] = {
643 [ C(OP_READ) ] = {
644 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
645 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
647 [ C(OP_WRITE) ] = {
648 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
649 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
651 [ C(OP_PREFETCH) ] = {
652 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
653 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
663 [ C(L1D) ] = {
664 [ C(OP_READ) ] = {
665 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
666 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
668 [ C(OP_WRITE) ] = {
669 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
670 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
672 [ C(OP_PREFETCH) ] = {
673 [ C(RESULT_ACCESS) ] = 0x0,
674 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
677 [ C(L1I ) ] = {
678 [ C(OP_READ) ] = {
679 [ C(RESULT_ACCESS) ] = 0x0,
680 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
682 [ C(OP_WRITE) ] = {
683 [ C(RESULT_ACCESS) ] = -1,
684 [ C(RESULT_MISS) ] = -1,
686 [ C(OP_PREFETCH) ] = {
687 [ C(RESULT_ACCESS) ] = 0x0,
688 [ C(RESULT_MISS) ] = 0x0,
691 [ C(LL ) ] = {
692 [ C(OP_READ) ] = {
694 [ C(RESULT_ACCESS) ] = 0x01b7,
696 [ C(RESULT_MISS) ] = 0x01b7,
698 [ C(OP_WRITE) ] = {
700 [ C(RESULT_ACCESS) ] = 0x01b7,
702 [ C(RESULT_MISS) ] = 0x01b7,
704 [ C(OP_PREFETCH) ] = {
706 [ C(RESULT_ACCESS) ] = 0x01b7,
708 [ C(RESULT_MISS) ] = 0x01b7,
711 [ C(DTLB) ] = {
712 [ C(OP_READ) ] = {
713 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
714 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
716 [ C(OP_WRITE) ] = {
717 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
718 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
720 [ C(OP_PREFETCH) ] = {
721 [ C(RESULT_ACCESS) ] = 0x0,
722 [ C(RESULT_MISS) ] = 0x0,
725 [ C(ITLB) ] = {
726 [ C(OP_READ) ] = {
727 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
728 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
730 [ C(OP_WRITE) ] = {
731 [ C(RESULT_ACCESS) ] = -1,
732 [ C(RESULT_MISS) ] = -1,
734 [ C(OP_PREFETCH) ] = {
735 [ C(RESULT_ACCESS) ] = -1,
736 [ C(RESULT_MISS) ] = -1,
739 [ C(BPU ) ] = {
740 [ C(OP_READ) ] = {
741 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
742 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
744 [ C(OP_WRITE) ] = {
745 [ C(RESULT_ACCESS) ] = -1,
746 [ C(RESULT_MISS) ] = -1,
748 [ C(OP_PREFETCH) ] = {
749 [ C(RESULT_ACCESS) ] = -1,
750 [ C(RESULT_MISS) ] = -1,
753 [ C(NODE) ] = {
754 [ C(OP_READ) ] = {
755 [ C(RESULT_ACCESS) ] = 0x01b7,
756 [ C(RESULT_MISS) ] = 0x01b7,
758 [ C(OP_WRITE) ] = {
759 [ C(RESULT_ACCESS) ] = 0x01b7,
760 [ C(RESULT_MISS) ] = 0x01b7,
762 [ C(OP_PREFETCH) ] = {
763 [ C(RESULT_ACCESS) ] = 0x01b7,
764 [ C(RESULT_MISS) ] = 0x01b7,
780 #define HSW_DEMAND_RFO BIT_ULL(1)
819 [ C(L1D ) ] = {
820 [ C(OP_READ) ] = {
821 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
822 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
824 [ C(OP_WRITE) ] = {
825 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
826 [ C(RESULT_MISS) ] = 0x0,
828 [ C(OP_PREFETCH) ] = {
829 [ C(RESULT_ACCESS) ] = 0x0,
830 [ C(RESULT_MISS) ] = 0x0,
833 [ C(L1I ) ] = {
834 [ C(OP_READ) ] = {
835 [ C(RESULT_ACCESS) ] = 0x0,
836 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */
838 [ C(OP_WRITE) ] = {
839 [ C(RESULT_ACCESS) ] = -1,
840 [ C(RESULT_MISS) ] = -1,
842 [ C(OP_PREFETCH) ] = {
843 [ C(RESULT_ACCESS) ] = 0x0,
844 [ C(RESULT_MISS) ] = 0x0,
847 [ C(LL ) ] = {
848 [ C(OP_READ) ] = {
849 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
850 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
852 [ C(OP_WRITE) ] = {
853 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
854 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
856 [ C(OP_PREFETCH) ] = {
857 [ C(RESULT_ACCESS) ] = 0x0,
858 [ C(RESULT_MISS) ] = 0x0,
861 [ C(DTLB) ] = {
862 [ C(OP_READ) ] = {
863 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
864 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
866 [ C(OP_WRITE) ] = {
867 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
868 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
870 [ C(OP_PREFETCH) ] = {
871 [ C(RESULT_ACCESS) ] = 0x0,
872 [ C(RESULT_MISS) ] = 0x0,
875 [ C(ITLB) ] = {
876 [ C(OP_READ) ] = {
877 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */
878 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */
880 [ C(OP_WRITE) ] = {
881 [ C(RESULT_ACCESS) ] = -1,
882 [ C(RESULT_MISS) ] = -1,
884 [ C(OP_PREFETCH) ] = {
885 [ C(RESULT_ACCESS) ] = -1,
886 [ C(RESULT_MISS) ] = -1,
889 [ C(BPU ) ] = {
890 [ C(OP_READ) ] = {
891 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
892 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
894 [ C(OP_WRITE) ] = {
895 [ C(RESULT_ACCESS) ] = -1,
896 [ C(RESULT_MISS) ] = -1,
898 [ C(OP_PREFETCH) ] = {
899 [ C(RESULT_ACCESS) ] = -1,
900 [ C(RESULT_MISS) ] = -1,
903 [ C(NODE) ] = {
904 [ C(OP_READ) ] = {
905 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
906 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
908 [ C(OP_WRITE) ] = {
909 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
910 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
912 [ C(OP_PREFETCH) ] = {
913 [ C(RESULT_ACCESS) ] = 0x0,
914 [ C(RESULT_MISS) ] = 0x0,
924 [ C(LL ) ] = {
925 [ C(OP_READ) ] = {
926 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
928 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
931 [ C(OP_WRITE) ] = {
932 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
934 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
937 [ C(OP_PREFETCH) ] = {
938 [ C(RESULT_ACCESS) ] = 0x0,
939 [ C(RESULT_MISS) ] = 0x0,
942 [ C(NODE) ] = {
943 [ C(OP_READ) ] = {
944 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
947 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
951 [ C(OP_WRITE) ] = {
952 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
955 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
959 [ C(OP_PREFETCH) ] = {
960 [ C(RESULT_ACCESS) ] = 0x0,
961 [ C(RESULT_MISS) ] = 0x0,
971 [ C(L1D) ] = {
972 [ C(OP_READ) ] = {
973 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
974 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
976 [ C(OP_WRITE) ] = {
977 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
978 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
980 [ C(OP_PREFETCH) ] = {
981 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
982 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
985 [ C(L1I ) ] = {
986 [ C(OP_READ) ] = {
987 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
988 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
990 [ C(OP_WRITE) ] = {
991 [ C(RESULT_ACCESS) ] = -1,
992 [ C(RESULT_MISS) ] = -1,
994 [ C(OP_PREFETCH) ] = {
995 [ C(RESULT_ACCESS) ] = 0x0,
996 [ C(RESULT_MISS) ] = 0x0,
999 [ C(LL ) ] = {
1000 [ C(OP_READ) ] = {
1002 [ C(RESULT_ACCESS) ] = 0x01b7,
1004 [ C(RESULT_MISS) ] = 0x01b7,
1010 [ C(OP_WRITE) ] = {
1012 [ C(RESULT_ACCESS) ] = 0x01b7,
1014 [ C(RESULT_MISS) ] = 0x01b7,
1016 [ C(OP_PREFETCH) ] = {
1018 [ C(RESULT_ACCESS) ] = 0x01b7,
1020 [ C(RESULT_MISS) ] = 0x01b7,
1023 [ C(DTLB) ] = {
1024 [ C(OP_READ) ] = {
1025 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1026 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1028 [ C(OP_WRITE) ] = {
1029 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1030 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1032 [ C(OP_PREFETCH) ] = {
1033 [ C(RESULT_ACCESS) ] = 0x0,
1034 [ C(RESULT_MISS) ] = 0x0,
1037 [ C(ITLB) ] = {
1038 [ C(OP_READ) ] = {
1039 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1040 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
1042 [ C(OP_WRITE) ] = {
1043 [ C(RESULT_ACCESS) ] = -1,
1044 [ C(RESULT_MISS) ] = -1,
1046 [ C(OP_PREFETCH) ] = {
1047 [ C(RESULT_ACCESS) ] = -1,
1048 [ C(RESULT_MISS) ] = -1,
1051 [ C(BPU ) ] = {
1052 [ C(OP_READ) ] = {
1053 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1054 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1056 [ C(OP_WRITE) ] = {
1057 [ C(RESULT_ACCESS) ] = -1,
1058 [ C(RESULT_MISS) ] = -1,
1060 [ C(OP_PREFETCH) ] = {
1061 [ C(RESULT_ACCESS) ] = -1,
1062 [ C(RESULT_MISS) ] = -1,
1065 [ C(NODE) ] = {
1066 [ C(OP_READ) ] = {
1067 [ C(RESULT_ACCESS) ] = 0x01b7,
1068 [ C(RESULT_MISS) ] = 0x01b7,
1070 [ C(OP_WRITE) ] = {
1071 [ C(RESULT_ACCESS) ] = 0x01b7,
1072 [ C(RESULT_MISS) ] = 0x01b7,
1074 [ C(OP_PREFETCH) ] = {
1075 [ C(RESULT_ACCESS) ] = 0x01b7,
1076 [ C(RESULT_MISS) ] = 0x01b7,
1086 #define NHM_DMND_DATA_RD (1 << 0)
1087 #define NHM_DMND_RFO (1 << 1)
1088 #define NHM_DMND_IFETCH (1 << 2)
1089 #define NHM_DMND_WB (1 << 3)
1090 #define NHM_PF_DATA_RD (1 << 4)
1091 #define NHM_PF_DATA_RFO (1 << 5)
1092 #define NHM_PF_IFETCH (1 << 6)
1093 #define NHM_OFFCORE_OTHER (1 << 7)
1094 #define NHM_UNCORE_HIT (1 << 8)
1095 #define NHM_OTHER_CORE_HIT_SNP (1 << 9)
1096 #define NHM_OTHER_CORE_HITM (1 << 10)
1098 #define NHM_REMOTE_CACHE_FWD (1 << 12)
1099 #define NHM_REMOTE_DRAM (1 << 13)
1100 #define NHM_LOCAL_DRAM (1 << 14)
1101 #define NHM_NON_DRAM (1 << 15)
1119 [ C(LL ) ] = {
1120 [ C(OP_READ) ] = {
1121 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
1122 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
1124 [ C(OP_WRITE) ] = {
1125 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
1126 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
1128 [ C(OP_PREFETCH) ] = {
1129 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
1130 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
1133 [ C(NODE) ] = {
1134 [ C(OP_READ) ] = {
1135 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
1136 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
1138 [ C(OP_WRITE) ] = {
1139 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
1140 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
1142 [ C(OP_PREFETCH) ] = {
1143 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
1144 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
1154 [ C(L1D) ] = {
1155 [ C(OP_READ) ] = {
1156 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1157 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
1159 [ C(OP_WRITE) ] = {
1160 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1161 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
1163 [ C(OP_PREFETCH) ] = {
1164 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1165 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1168 [ C(L1I ) ] = {
1169 [ C(OP_READ) ] = {
1170 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1171 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1173 [ C(OP_WRITE) ] = {
1174 [ C(RESULT_ACCESS) ] = -1,
1175 [ C(RESULT_MISS) ] = -1,
1177 [ C(OP_PREFETCH) ] = {
1178 [ C(RESULT_ACCESS) ] = 0x0,
1179 [ C(RESULT_MISS) ] = 0x0,
1182 [ C(LL ) ] = {
1183 [ C(OP_READ) ] = {
1185 [ C(RESULT_ACCESS) ] = 0x01b7,
1187 [ C(RESULT_MISS) ] = 0x01b7,
1193 [ C(OP_WRITE) ] = {
1195 [ C(RESULT_ACCESS) ] = 0x01b7,
1197 [ C(RESULT_MISS) ] = 0x01b7,
1199 [ C(OP_PREFETCH) ] = {
1201 [ C(RESULT_ACCESS) ] = 0x01b7,
1203 [ C(RESULT_MISS) ] = 0x01b7,
1206 [ C(DTLB) ] = {
1207 [ C(OP_READ) ] = {
1208 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1209 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1211 [ C(OP_WRITE) ] = {
1212 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1213 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1215 [ C(OP_PREFETCH) ] = {
1216 [ C(RESULT_ACCESS) ] = 0x0,
1217 [ C(RESULT_MISS) ] = 0x0,
1220 [ C(ITLB) ] = {
1221 [ C(OP_READ) ] = {
1222 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1223 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
1225 [ C(OP_WRITE) ] = {
1226 [ C(RESULT_ACCESS) ] = -1,
1227 [ C(RESULT_MISS) ] = -1,
1229 [ C(OP_PREFETCH) ] = {
1230 [ C(RESULT_ACCESS) ] = -1,
1231 [ C(RESULT_MISS) ] = -1,
1234 [ C(BPU ) ] = {
1235 [ C(OP_READ) ] = {
1236 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1237 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1239 [ C(OP_WRITE) ] = {
1240 [ C(RESULT_ACCESS) ] = -1,
1241 [ C(RESULT_MISS) ] = -1,
1243 [ C(OP_PREFETCH) ] = {
1244 [ C(RESULT_ACCESS) ] = -1,
1245 [ C(RESULT_MISS) ] = -1,
1248 [ C(NODE) ] = {
1249 [ C(OP_READ) ] = {
1250 [ C(RESULT_ACCESS) ] = 0x01b7,
1251 [ C(RESULT_MISS) ] = 0x01b7,
1253 [ C(OP_WRITE) ] = {
1254 [ C(RESULT_ACCESS) ] = 0x01b7,
1255 [ C(RESULT_MISS) ] = 0x01b7,
1257 [ C(OP_PREFETCH) ] = {
1258 [ C(RESULT_ACCESS) ] = 0x01b7,
1259 [ C(RESULT_MISS) ] = 0x01b7,
1269 [ C(L1D) ] = {
1270 [ C(OP_READ) ] = {
1271 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
1272 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
1274 [ C(OP_WRITE) ] = {
1275 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
1276 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
1278 [ C(OP_PREFETCH) ] = {
1279 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
1280 [ C(RESULT_MISS) ] = 0,
1283 [ C(L1I ) ] = {
1284 [ C(OP_READ) ] = {
1285 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
1286 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
1288 [ C(OP_WRITE) ] = {
1289 [ C(RESULT_ACCESS) ] = -1,
1290 [ C(RESULT_MISS) ] = -1,
1292 [ C(OP_PREFETCH) ] = {
1293 [ C(RESULT_ACCESS) ] = 0,
1294 [ C(RESULT_MISS) ] = 0,
1297 [ C(LL ) ] = {
1298 [ C(OP_READ) ] = {
1299 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1300 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1302 [ C(OP_WRITE) ] = {
1303 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1304 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1306 [ C(OP_PREFETCH) ] = {
1307 [ C(RESULT_ACCESS) ] = 0,
1308 [ C(RESULT_MISS) ] = 0,
1311 [ C(DTLB) ] = {
1312 [ C(OP_READ) ] = {
1313 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1314 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
1316 [ C(OP_WRITE) ] = {
1317 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1318 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
1320 [ C(OP_PREFETCH) ] = {
1321 [ C(RESULT_ACCESS) ] = 0,
1322 [ C(RESULT_MISS) ] = 0,
1325 [ C(ITLB) ] = {
1326 [ C(OP_READ) ] = {
1327 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1328 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
1330 [ C(OP_WRITE) ] = {
1331 [ C(RESULT_ACCESS) ] = -1,
1332 [ C(RESULT_MISS) ] = -1,
1334 [ C(OP_PREFETCH) ] = {
1335 [ C(RESULT_ACCESS) ] = -1,
1336 [ C(RESULT_MISS) ] = -1,
1339 [ C(BPU ) ] = {
1340 [ C(OP_READ) ] = {
1341 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1342 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1344 [ C(OP_WRITE) ] = {
1345 [ C(RESULT_ACCESS) ] = -1,
1346 [ C(RESULT_MISS) ] = -1,
1348 [ C(OP_PREFETCH) ] = {
1349 [ C(RESULT_ACCESS) ] = -1,
1350 [ C(RESULT_MISS) ] = -1,
1360 [ C(L1D) ] = {
1361 [ C(OP_READ) ] = {
1362 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
1363 [ C(RESULT_MISS) ] = 0,
1365 [ C(OP_WRITE) ] = {
1366 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
1367 [ C(RESULT_MISS) ] = 0,
1369 [ C(OP_PREFETCH) ] = {
1370 [ C(RESULT_ACCESS) ] = 0x0,
1371 [ C(RESULT_MISS) ] = 0,
1374 [ C(L1I ) ] = {
1375 [ C(OP_READ) ] = {
1376 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1377 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1379 [ C(OP_WRITE) ] = {
1380 [ C(RESULT_ACCESS) ] = -1,
1381 [ C(RESULT_MISS) ] = -1,
1383 [ C(OP_PREFETCH) ] = {
1384 [ C(RESULT_ACCESS) ] = 0,
1385 [ C(RESULT_MISS) ] = 0,
1388 [ C(LL ) ] = {
1389 [ C(OP_READ) ] = {
1390 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1391 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1393 [ C(OP_WRITE) ] = {
1394 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1395 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1397 [ C(OP_PREFETCH) ] = {
1398 [ C(RESULT_ACCESS) ] = 0,
1399 [ C(RESULT_MISS) ] = 0,
1402 [ C(DTLB) ] = {
1403 [ C(OP_READ) ] = {
1404 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
1405 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
1407 [ C(OP_WRITE) ] = {
1408 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
1409 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
1411 [ C(OP_PREFETCH) ] = {
1412 [ C(RESULT_ACCESS) ] = 0,
1413 [ C(RESULT_MISS) ] = 0,
1416 [ C(ITLB) ] = {
1417 [ C(OP_READ) ] = {
1418 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1419 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
1421 [ C(OP_WRITE) ] = {
1422 [ C(RESULT_ACCESS) ] = -1,
1423 [ C(RESULT_MISS) ] = -1,
1425 [ C(OP_PREFETCH) ] = {
1426 [ C(RESULT_ACCESS) ] = -1,
1427 [ C(RESULT_MISS) ] = -1,
1430 [ C(BPU ) ] = {
1431 [ C(OP_READ) ] = {
1432 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1433 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1435 [ C(OP_WRITE) ] = {
1436 [ C(RESULT_ACCESS) ] = -1,
1437 [ C(RESULT_MISS) ] = -1,
1439 [ C(OP_PREFETCH) ] = {
1440 [ C(RESULT_ACCESS) ] = -1,
1441 [ C(RESULT_MISS) ] = -1,
1490 [ C(LL ) ] = {
1491 [ C(OP_READ) ] = {
1492 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
1493 [ C(RESULT_MISS) ] = 0,
1495 [ C(OP_WRITE) ] = {
1496 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1497 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1499 [ C(OP_PREFETCH) ] = {
1500 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1501 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1511 [ C(L1D) ] = {
1512 [ C(OP_READ) ] = {
1513 [ C(RESULT_ACCESS) ] = 0,
1514 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */
1516 [ C(OP_WRITE) ] = {
1517 [ C(RESULT_ACCESS) ] = 0,
1518 [ C(RESULT_MISS) ] = 0,
1520 [ C(OP_PREFETCH) ] = {
1521 [ C(RESULT_ACCESS) ] = 0,
1522 [ C(RESULT_MISS) ] = 0,
1525 [ C(L1I ) ] = {
1526 [ C(OP_READ) ] = {
1527 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
1528 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */
1530 [ C(OP_WRITE) ] = {
1531 [ C(RESULT_ACCESS) ] = -1,
1532 [ C(RESULT_MISS) ] = -1,
1534 [ C(OP_PREFETCH) ] = {
1535 [ C(RESULT_ACCESS) ] = 0,
1536 [ C(RESULT_MISS) ] = 0,
1539 [ C(LL ) ] = {
1540 [ C(OP_READ) ] = {
1542 [ C(RESULT_ACCESS) ] = 0x01b7,
1543 [ C(RESULT_MISS) ] = 0,
1545 [ C(OP_WRITE) ] = {
1547 [ C(RESULT_ACCESS) ] = 0x01b7,
1549 [ C(RESULT_MISS) ] = 0x01b7,
1551 [ C(OP_PREFETCH) ] = {
1553 [ C(RESULT_ACCESS) ] = 0x01b7,
1555 [ C(RESULT_MISS) ] = 0x01b7,
1558 [ C(DTLB) ] = {
1559 [ C(OP_READ) ] = {
1560 [ C(RESULT_ACCESS) ] = 0,
1561 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */
1563 [ C(OP_WRITE) ] = {
1564 [ C(RESULT_ACCESS) ] = 0,
1565 [ C(RESULT_MISS) ] = 0,
1567 [ C(OP_PREFETCH) ] = {
1568 [ C(RESULT_ACCESS) ] = 0,
1569 [ C(RESULT_MISS) ] = 0,
1572 [ C(ITLB) ] = {
1573 [ C(OP_READ) ] = {
1574 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1575 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */
1577 [ C(OP_WRITE) ] = {
1578 [ C(RESULT_ACCESS) ] = -1,
1579 [ C(RESULT_MISS) ] = -1,
1581 [ C(OP_PREFETCH) ] = {
1582 [ C(RESULT_ACCESS) ] = -1,
1583 [ C(RESULT_MISS) ] = -1,
1586 [ C(BPU ) ] = {
1587 [ C(OP_READ) ] = {
1588 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1589 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1591 [ C(OP_WRITE) ] = {
1592 [ C(RESULT_ACCESS) ] = -1,
1593 [ C(RESULT_MISS) ] = -1,
1595 [ C(OP_PREFETCH) ] = {
1596 [ C(RESULT_ACCESS) ] = -1,
1597 [ C(RESULT_MISS) ] = -1,
1631 #define GLM_DEMAND_RFO BIT_ULL(1)
1645 [C(L1D)] = {
1646 [C(OP_READ)] = {
1647 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1648 [C(RESULT_MISS)] = 0x0,
1650 [C(OP_WRITE)] = {
1651 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1652 [C(RESULT_MISS)] = 0x0,
1654 [C(OP_PREFETCH)] = {
1655 [C(RESULT_ACCESS)] = 0x0,
1656 [C(RESULT_MISS)] = 0x0,
1659 [C(L1I)] = {
1660 [C(OP_READ)] = {
1661 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
1662 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
1664 [C(OP_WRITE)] = {
1665 [C(RESULT_ACCESS)] = -1,
1666 [C(RESULT_MISS)] = -1,
1668 [C(OP_PREFETCH)] = {
1669 [C(RESULT_ACCESS)] = 0x0,
1670 [C(RESULT_MISS)] = 0x0,
1673 [C(LL)] = {
1674 [C(OP_READ)] = {
1675 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1676 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1678 [C(OP_WRITE)] = {
1679 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1680 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1682 [C(OP_PREFETCH)] = {
1683 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1684 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1687 [C(DTLB)] = {
1688 [C(OP_READ)] = {
1689 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1690 [C(RESULT_MISS)] = 0x0,
1692 [C(OP_WRITE)] = {
1693 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1694 [C(RESULT_MISS)] = 0x0,
1696 [C(OP_PREFETCH)] = {
1697 [C(RESULT_ACCESS)] = 0x0,
1698 [C(RESULT_MISS)] = 0x0,
1701 [C(ITLB)] = {
1702 [C(OP_READ)] = {
1703 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
1704 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
1706 [C(OP_WRITE)] = {
1707 [C(RESULT_ACCESS)] = -1,
1708 [C(RESULT_MISS)] = -1,
1710 [C(OP_PREFETCH)] = {
1711 [C(RESULT_ACCESS)] = -1,
1712 [C(RESULT_MISS)] = -1,
1715 [C(BPU)] = {
1716 [C(OP_READ)] = {
1717 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1718 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1720 [C(OP_WRITE)] = {
1721 [C(RESULT_ACCESS)] = -1,
1722 [C(RESULT_MISS)] = -1,
1724 [C(OP_PREFETCH)] = {
1725 [C(RESULT_ACCESS)] = -1,
1726 [C(RESULT_MISS)] = -1,
1735 [C(LL)] = {
1736 [C(OP_READ)] = {
1737 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
1739 [C(RESULT_MISS)] = GLM_DEMAND_READ|
1742 [C(OP_WRITE)] = {
1743 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
1745 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
1748 [C(OP_PREFETCH)] = {
1749 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH|
1751 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH|
1761 [C(L1D)] = {
1762 [C(OP_READ)] = {
1763 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1764 [C(RESULT_MISS)] = 0x0,
1766 [C(OP_WRITE)] = {
1767 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1768 [C(RESULT_MISS)] = 0x0,
1770 [C(OP_PREFETCH)] = {
1771 [C(RESULT_ACCESS)] = 0x0,
1772 [C(RESULT_MISS)] = 0x0,
1775 [C(L1I)] = {
1776 [C(OP_READ)] = {
1777 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
1778 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
1780 [C(OP_WRITE)] = {
1781 [C(RESULT_ACCESS)] = -1,
1782 [C(RESULT_MISS)] = -1,
1784 [C(OP_PREFETCH)] = {
1785 [C(RESULT_ACCESS)] = 0x0,
1786 [C(RESULT_MISS)] = 0x0,
1789 [C(LL)] = {
1790 [C(OP_READ)] = {
1791 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1792 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1794 [C(OP_WRITE)] = {
1795 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1796 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1798 [C(OP_PREFETCH)] = {
1799 [C(RESULT_ACCESS)] = 0x0,
1800 [C(RESULT_MISS)] = 0x0,
1803 [C(DTLB)] = {
1804 [C(OP_READ)] = {
1805 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1806 [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
1808 [C(OP_WRITE)] = {
1809 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1810 [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
1812 [C(OP_PREFETCH)] = {
1813 [C(RESULT_ACCESS)] = 0x0,
1814 [C(RESULT_MISS)] = 0x0,
1817 [C(ITLB)] = {
1818 [C(OP_READ)] = {
1819 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
1820 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
1822 [C(OP_WRITE)] = {
1823 [C(RESULT_ACCESS)] = -1,
1824 [C(RESULT_MISS)] = -1,
1826 [C(OP_PREFETCH)] = {
1827 [C(RESULT_ACCESS)] = -1,
1828 [C(RESULT_MISS)] = -1,
1831 [C(BPU)] = {
1832 [C(OP_READ)] = {
1833 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1834 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1836 [C(OP_WRITE)] = {
1837 [C(RESULT_ACCESS)] = -1,
1838 [C(RESULT_MISS)] = -1,
1840 [C(OP_PREFETCH)] = {
1841 [C(RESULT_ACCESS)] = -1,
1842 [C(RESULT_MISS)] = -1,
1851 [C(LL)] = {
1852 [C(OP_READ)] = {
1853 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
1855 [C(RESULT_MISS)] = GLM_DEMAND_READ|
1858 [C(OP_WRITE)] = {
1859 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
1861 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
1864 [C(OP_PREFETCH)] = {
1865 [C(RESULT_ACCESS)] = 0x0,
1866 [C(RESULT_MISS)] = 0x0,
1883 [C(LL)] = {
1884 [C(OP_READ)] = {
1885 [C(RESULT_ACCESS)] = TNT_DEMAND_READ|
1887 [C(RESULT_MISS)] = TNT_DEMAND_READ|
1890 [C(OP_WRITE)] = {
1891 [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE|
1893 [C(RESULT_MISS)] = TNT_DEMAND_WRITE|
1896 [C(OP_PREFETCH)] = {
1897 [C(RESULT_ACCESS)] = 0x0,
1898 [C(RESULT_MISS)] = 0x0,
1930 [C(LL)] = {
1931 [C(OP_READ)] = {
1932 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS,
1933 [C(RESULT_MISS)] = 0,
1935 [C(OP_WRITE)] = {
1936 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS,
1937 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS,
1939 [C(OP_PREFETCH)] = {
1940 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS,
1941 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS,
2037 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL; in intel_pmu_nhm_workaround()
2047 * A) To reduce MSR operations, we don't run step 1) as they in intel_pmu_nhm_workaround()
2051 * C) With step 5), we do clear only when the PERFEVTSELx is in intel_pmu_nhm_workaround()
2207 case 0 ... INTEL_PMC_IDX_FIXED - 1: in intel_pmu_disable_event()
2211 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: in intel_pmu_disable_event()
2316 * may be reduced from 1 to 0. If so, the bad_spec event value in __icl_update_topdown_event()
2336 for_each_set_bit(idx, cpuc->active_mask, INTEL_PMC_IDX_TD_BE_BOUND + 1) { in update_saved_topdown_regs()
2367 for_each_set_bit(idx, cpuc->active_mask, INTEL_PMC_IDX_TD_BE_BOUND + 1) { in icl_update_topdown_event()
2494 case 0 ... INTEL_PMC_IDX_FIXED - 1: in intel_pmu_enable_event()
2498 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: in intel_pmu_enable_event()
2707 return 1; in intel_perf_counter_freezing_setup()
2744 WARN(1, "perfevents: irq loop stuck!\n"); in intel_pmu_handle_irq_v4()
2829 WARN(1, "perfevents: irq loop stuck!\n"); in intel_pmu_handle_irq()
2878 struct event_constraint *c = &vlbr_constraint; in intel_vlbr_constraints() local
2880 if (unlikely(constraint_match(c, event->hw.config))) in intel_vlbr_constraints()
2881 return c; in intel_vlbr_constraints()
2932 struct event_constraint *c = &emptyconstraint; in __intel_shared_reg_get_constraints() local
2975 reg->alloc = 1; in __intel_shared_reg_get_constraints()
2989 c = NULL; in __intel_shared_reg_get_constraints()
2999 return c; in __intel_shared_reg_get_constraints()
3032 struct event_constraint *c = NULL, *d; in intel_shared_regs_constraints() local
3037 c = __intel_shared_reg_get_constraints(cpuc, event, xreg); in intel_shared_regs_constraints()
3038 if (c == &emptyconstraint) in intel_shared_regs_constraints()
3039 return c; in intel_shared_regs_constraints()
3046 c = d; in intel_shared_regs_constraints()
3049 return c; in intel_shared_regs_constraints()
3056 struct event_constraint *c; in x86_get_event_constraints() local
3059 for_each_event_constraint(c, x86_pmu.event_constraints) { in x86_get_event_constraints()
3060 if (constraint_match(c, event->hw.config)) { in x86_get_event_constraints()
3061 event->hw.flags |= c->flags; in x86_get_event_constraints()
3062 return c; in x86_get_event_constraints()
3074 struct event_constraint *c; in __intel_get_event_constraints() local
3076 c = intel_vlbr_constraints(event); in __intel_get_event_constraints()
3077 if (c) in __intel_get_event_constraints()
3078 return c; in __intel_get_event_constraints()
3080 c = intel_bts_constraints(event); in __intel_get_event_constraints()
3081 if (c) in __intel_get_event_constraints()
3082 return c; in __intel_get_event_constraints()
3084 c = intel_shared_regs_constraints(cpuc, event); in __intel_get_event_constraints()
3085 if (c) in __intel_get_event_constraints()
3086 return c; in __intel_get_event_constraints()
3088 c = intel_pebs_constraints(event); in __intel_get_event_constraints()
3089 if (c) in __intel_get_event_constraints()
3090 return c; in __intel_get_event_constraints()
3128 struct event_constraint *c = cpuc->event_constraint[idx]; in intel_commit_scheduling() local
3138 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) in intel_commit_scheduling()
3145 if (c->flags & PERF_X86_EVENT_EXCL) in intel_commit_scheduling()
3179 dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx) in dyn_constraint() argument
3183 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) { in dyn_constraint()
3195 *cx = *c; in dyn_constraint()
3201 c = cx; in dyn_constraint()
3204 return c; in dyn_constraint()
3209 int idx, struct event_constraint *c) in intel_get_excl_constraints() argument
3221 return c; in intel_get_excl_constraints()
3227 return c; in intel_get_excl_constraints()
3237 c = dyn_constraint(cpuc, c, idx); in intel_get_excl_constraints()
3249 xlo = &excl_cntrs->states[tid ^ 1]; in intel_get_excl_constraints()
3255 is_excl = c->flags & PERF_X86_EVENT_EXCL; in intel_get_excl_constraints()
3259 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1); in intel_get_excl_constraints()
3270 w = c->weight; in intel_get_excl_constraints()
3271 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) { in intel_get_excl_constraints()
3278 __clear_bit(i, c->idxmsk); in intel_get_excl_constraints()
3288 __clear_bit(i, c->idxmsk); in intel_get_excl_constraints()
3300 c = &emptyconstraint; in intel_get_excl_constraints()
3302 c->weight = w; in intel_get_excl_constraints()
3304 return c; in intel_get_excl_constraints()
3429 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); in intel_pebs_aliases_core2()
3457 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16); in intel_pebs_aliases_snb()
3478 * only programmed on counter 1, but that seems like an in intel_pebs_aliases_precdist()
3481 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16); in intel_pebs_aliases_precdist()
3701 *nr = 1; in intel_guest_get_msrs()
3712 arr[1].msr = MSR_IA32_PEBS_ENABLE; in intel_guest_get_msrs()
3713 arr[1].host = cpuc->pebs_enabled; in intel_guest_get_msrs()
3714 arr[1].guest = 0; in intel_guest_get_msrs()
3824 struct event_constraint *c; in hsw_get_event_constraints() local
3826 c = intel_get_event_constraints(cpuc, idx, event); in hsw_get_event_constraints()
3830 if (c->idxmsk64 & (1U << 2)) in hsw_get_event_constraints()
3835 return c; in hsw_get_event_constraints()
3857 struct event_constraint *c; in glp_get_event_constraints() local
3863 c = intel_get_event_constraints(cpuc, idx, event); in glp_get_event_constraints()
3865 return c; in glp_get_event_constraints()
3872 struct event_constraint *c; in tnt_get_event_constraints() local
3886 c = intel_get_event_constraints(cpuc, idx, event); in tnt_get_event_constraints()
3888 return c; in tnt_get_event_constraints()
3897 struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event); in tfa_get_event_constraints() local
3902 if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) { in tfa_get_event_constraints()
3903 c = dyn_constraint(cpuc, c, idx); in tfa_get_event_constraints()
3904 c->idxmsk64 &= ~(1ULL << 3); in tfa_get_event_constraints()
3905 c->weight--; in tfa_get_event_constraints()
3908 return c; in tfa_get_event_constraints()
3983 regs->core_id = -1; in allocate_shared_regs()
3990 struct intel_excl_cntrs *c; in allocate_excl_cntrs() local
3992 c = kzalloc_node(sizeof(struct intel_excl_cntrs), in allocate_excl_cntrs()
3994 if (c) { in allocate_excl_cntrs()
3995 raw_spin_lock_init(&c->lock); in allocate_excl_cntrs()
3996 c->core_id = -1; in allocate_excl_cntrs()
3998 return c; in allocate_excl_cntrs()
4080 if (x86_pmu.version > 1) in intel_pmu_cpu_starting()
4093 x86_pmu.intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS); in intel_pmu_cpu_starting()
4121 struct intel_excl_cntrs *c; in intel_pmu_cpu_starting() local
4124 c = sibling->excl_cntrs; in intel_pmu_cpu_starting()
4125 if (c && c->core_id == core_id) { in intel_pmu_cpu_starting()
4126 cpuc->kfree_on_online[1] = cpuc->excl_cntrs; in intel_pmu_cpu_starting()
4127 cpuc->excl_cntrs = c; in intel_pmu_cpu_starting()
4129 cpuc->excl_thread_id = 1; in intel_pmu_cpu_starting()
4140 struct intel_excl_cntrs *c; in free_excl_cntrs() local
4142 c = cpuc->excl_cntrs; in free_excl_cntrs()
4143 if (c) { in free_excl_cntrs()
4144 if (c->core_id == -1 || --c->refcnt == 0) in free_excl_cntrs()
4145 kfree(c); in free_excl_cntrs()
4167 if (pc->core_id == -1 || --pc->refcnt == 0) in intel_cpuc_finish()
4260 .apic = 1,
4265 * so we install an artificial 1<<31 period regardless of
4268 .max_period = (1ULL<<31) - 1,
4278 * together with PMU version 1 and thus be using core_pmu with
4311 .apic = 1,
4315 * so we install an artificial 1<<31 period regardless of
4318 .max_period = (1ULL << 31) - 1,
4373 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_L, 1, 0x0000001e),
4374 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_G, 1, 0x00000015),
4378 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_G, 1, 0x00000014),
4437 x86_pmu.pebs_broken = 1; in intel_snb_check_microcode()
4554 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_D, 1, 0x00000028),
4555 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_PLUS, 1, 0x00000028),
4618 EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1");
4619 EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1");
4712 if (val > 1) in freeze_on_smi_store()
4723 on_each_cpu(flip_smm_bit, &val, 1); in freeze_on_smi_store()
4768 on_each_cpu(update_tfa_sched, NULL, 1); in set_sysctl_tfa()
4914 struct event_constraint *c; in intel_pmu_init() local
4950 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; in intel_pmu_init()
4961 if (version > 1) { in intel_pmu_init()
5043 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
5044 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ in intel_pmu_init()
5046 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); in intel_pmu_init()
5050 x86_pmu.pebs_no_tlb = 1; in intel_pmu_init()
5161 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; in intel_pmu_init()
5201 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
5202 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ in intel_pmu_init()
5204 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); in intel_pmu_init()
5239 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ in intel_pmu_init()
5241 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
5242 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/ in intel_pmu_init()
5244 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
5258 …hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MI… in intel_pmu_init()
5280 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ in intel_pmu_init()
5282 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
5334 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ | in intel_pmu_init()
5336 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS| in intel_pmu_init()
5338 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ| in intel_pmu_init()
5340 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE| in intel_pmu_init()
5401 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */ in intel_pmu_init()
5403 "event=0xd,umask=0x1,cmask=1"; in intel_pmu_init()
5405 "event=0xd,umask=0x1,cmask=1,any=1"; in intel_pmu_init()
5448 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; in intel_pmu_init()
5478 case 1: in intel_pmu_init()
5506 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", in intel_pmu_init()
5510 x86_pmu.intel_ctrl = (1ULL << x86_pmu.num_counters) - 1; in intel_pmu_init()
5513 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", in intel_pmu_init()
5519 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED; in intel_pmu_init()
5530 for_each_event_constraint(c, x86_pmu.event_constraints) { in intel_pmu_init()
5535 if (c->idxmsk64 & INTEL_PMC_MSK_TOPDOWN) { in intel_pmu_init()
5536 c->weight = hweight64(c->idxmsk64); in intel_pmu_init()
5540 if (c->cmask == FIXED_EVENT_FLAGS in intel_pmu_init()
5541 && c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES) { in intel_pmu_init()
5542 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1; in intel_pmu_init()
5544 c->idxmsk64 &= in intel_pmu_init()
5546 c->weight = hweight64(c->idxmsk64); in intel_pmu_init()
5583 x86_pmu.max_period = x86_pmu.cntval_mask >> 1; in intel_pmu_init()
5596 x86_pmu.intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS; in intel_pmu_init()
5609 int c; in fixup_ht_bug() local
5616 if (topology_max_smt_threads() > 1) { in fixup_ht_bug()
5633 for_each_online_cpu(c) in fixup_ht_bug()
5634 free_excl_cntrs(&per_cpu(cpu_hw_events, c)); in fixup_ht_bug()