boot/compressed/head_64.S

1 /* SPDX-License-Identifier: GPL-2.0 */
9  *  head.S contains the 32-bit startup code.
11  * NOTE!!! Startup happens at absolute address 0x00001000, which is also where
12  * the page directory will exist. The startup code will be overwritten by
14  * kernel it will end up at 0x1000 + 1Mb I hope so as I assume this. - AC]
33 #include <asm/processor-flags.h>
34 #include <asm/asm-offsets.h>
50  * from startup_32. This is the same as the link-time virtual address of X,
52  * assembler/linker that we do not want the actual run-time address of X. This
53  * prevents the linker from trying to create unwanted run-time relocation
56  * A reference X(%reg) will result in the link-time VA of X being stored with
57  * the instruction, and a run-time R_X86_64_RELATIVE relocation entry that
58  * adds the 64-bit base address where the kernel is loaded.
60  * Replacing it with (X-startup_32)(%reg) results in the offset being stored,
61  * and no run-time relocation.
64  * the run-time address of startup_32 [i.e. rva(X)(%reg)], or as an immediate
71 #define rva(X) ((X) - startup_32)
88  * address we are running at.  The reserved chunk of the real-mode
123  * for safe in-place decompression.
135  *	image_offset = startup_32 - image_base
252 	 * efi_pe_entry uses MS calling convention, which requires 32 bytes of
260 	movl	%edi, %ecx			// MS calling convention
341 	 * We cannot rely on the calculation done in 32-bit mode, since we
342 	 * may have been invoked via the 64-bit entry point.
347 	leaq	startup_32(%rip) /* - $startup_32 */, %rbp
355  *	image_offset = startup_32 - image_base
382 	 * At this point we are in long mode with 4-level paging enabled,
383 	 * but we might want to enable 5-level paging or vice versa.
390 	 * 4- to 5-level paging for cases when the bootloader puts the kernel
391 	 * above 4G, but didn't enable 5-level paging for us.
393 	 * The same trampoline can be used to switch from 5- to 4-level paging
394 	 * mode, like when starting 4-level paging kernel via kexec() when
395 	 * original kernel worked in 5-level paging mode.
398 	 * memory as we don't have a way to load 64-bit values into CR3 in
399 	 * 32-bit mode.
406 	/* Make sure we have GDT with 32-bit code segment */
425 	 * enable 5-level paging.
427 	 * paging_prepare() returns a two-quadword structure which lands
429 	 *   - Address of the trampoline is returned in RAX.
430 	 *   - Non zero RDX means trampoline needs to enable 5-level
456 	/* Restore the stack, the 32-bit trampoline uses its own stack */
482 	leaq	(_bss-8)(%rip), %rsi
483 	leaq	rva(_bss-8)(%rbx), %rdi
484 	movl	$(_bss - startup_32), %ecx
537  * page-table setup code below. When the guest also has SEV-ES enabled
539  * handler can't map its GHCB because the page-table is not set up yet.
542  * page-table.
574  * This is the 32-bit trampoline that will be copied over to low memory.
578  * Non zero RDX means trampoline needs to enable 5-level paging.
598 	/* We want 5-level paging: don't touch CR3 if it already points to 5-level page tables */
604 	/* We want 4-level paging: don't touch CR3 if it already points to 4-level page tables */
632 	leal	.Lpaging_enabled - trampoline_32bit_src + TRAMPOLINE_32BIT_CODE_OFFSET(%ecx), %eax
660 	/* This isn't an x86-64 CPU, so hang intentionally, we cannot continue */
670 	.word	gdt_end - gdt - 1
671 	.quad   gdt - gdt64
675 	.word	gdt_end - gdt - 1
686 	.word	boot_idt_end - boot_idt - 1
720 	pushl	%ebx				// save callee-save registers
733 	leal	-4(%ebp), %eax
742 	 *   handle             <-- 16-byte aligned on entry by ABI
745 	 *   loaded_image       <-- local variable
746 	 *   saved %ebx		<-- 16-byte aligned here
750 	 *   handle             <-- 16-byte aligned for call to handle_protocol
754 	movl	ST32_boottime(%eax), %eax	// sys_table->boottime
755 	call	*BS32_handle_protocol(%eax)	// sys_table->boottime->handle_protocol
762 	movl	-4(%ebp), %esi			// loaded_image
763 	movl	LI32_image_base(%esi), %esi	// loaded_image->image_base
767 	 * use it before we get to the 64-bit efi_pe_entry() in C code.
773 2:	popl	%edi				// restore callee-save registers