sparc/lib/M7memset.S

15  * Fast assembler language version of the following C-program for memset
16  * which represents the `standard' for the C-library.
25  *		} while (--n != 0);
35  *	Then store as many 4-byte chunks, followed by trailing bytes.
39  *      	store 8-bytes chunks to align the address on 64 byte boundary
42  *			64-byte cache line to zero which will also clear the
43  *			other seven long words of the cache line.
47  *              	ST_CHUNK cache lines (64 bytes each) before the main
49  *              	In the main loop, continue pre-setting the first long
50  *              	word of each cache line ST_CHUNK lines in advance while
52  * 			cache line until fewer than ST_CHUNK*64 bytes remain.
53  *			Then set the remaining seven long words of each cache
56  *       	store remaining data in 64-byte chunks until less than
59  *       Store as many 8-byte chunks, followed by trailing bytes.
61  * BIS = Block Init Store
62  *   Doing the advance store of the first element of the cache line
63  *   initiates the displacement of a cache line while only using a single
76  * ASI_STBI_P marks the cache line as "least recently used"
78  * of being pushed out of the cache between the first initializing
80  * Thus, we use ASI_STBIMRU_P which marks the cache line as
81  * "most recently used" for all but the last store to the cache line.
109 	.size		M7clear_page,.-M7clear_page
110 	.size		M7clear_user_page,.-M7clear_user_page
117 M7bzero:		/* bzero(dest, size) */
122 	.size		M7bzero,.-M7bzero
146 	 sub     %o3, 8, %o3             ! -(bytes till long word aligned)
149 	! Set -(%o3) bytes till sp1 long word aligned
161 	andcc   %o5, 63, %o3            ! is sp1 block aligned?
162 	bz,pt   %xcc, .blkwr            ! now block aligned
163 	 sub     %o3, 64, %o3            ! o3 is -(bytes till block aligned)
166 	! Store -(%o3) bytes till dst is block (64 byte) aligned.
175 	! Now sp1 is block aligned
177 	andn    %o2, 63, %o4            ! calculate size of blocks in bytes
184 	                                ! must be > pre-cleared lines
187 	! initial cache-clearing stores
201 	stxa    %o1, [%o5+8-128]%asi
203 	 stxa    %o1, [%o5+8-64]%asi
217 	stxa    %o1, [%o5-8]%asi
222 	! setting the first long word of each cache line in advance
241 	stxa    %o1, [%o5-8]%asi
249 	! For each 64 byte cache line, single STBI to first element
284 	membar  #StoreStore             ! required by use of Block Store Init
299 	stx     %o1, [%o5-16]
301 	 stx     %o1, [%o5-8]
333 	st      %o1, [%o5]              ! 4-byte writing loop
352 	.size		M7memset,.-M7memset