Lines Matching +full:0 +full:x48
54 /* When an irrecoverable trap occurs at tl > 0, the trap entry
73 printk(KERN_EMERG "TRAPLOG: Error at trap level 0x%lx, " in dump_tl1_traplog()
77 for (i = 0; i < limit; i++) { in dump_tl1_traplog()
93 0, lvl, SIGTRAP) == NOTIFY_STOP) in bad_trap()
96 if (lvl < 0x100) { in bad_trap()
101 lvl -= 0x100; in bad_trap()
107 regs->tpc &= 0xffffffff; in bad_trap()
108 regs->tnpc &= 0xffffffff; in bad_trap()
119 0, lvl, SIGTRAP) == NOTIFY_STOP) in bad_trap_tl1()
124 sprintf (buffer, "Bad trap %lx at tl>0", lvl); in bad_trap_tl1()
152 ret = 0; in sprintf_dimm()
163 int ret = 0; in register_dimm_printer()
192 0, 0x8, SIGTRAP) == NOTIFY_STOP) in spitfire_insn_access_exception()
201 regs->tpc &= 0xffffffff; in spitfire_insn_access_exception()
202 regs->tnpc &= 0xffffffff; in spitfire_insn_access_exception()
205 (void __user *)regs->tpc, 0); in spitfire_insn_access_exception()
213 0, 0x8, SIGTRAP) == NOTIFY_STOP) in spitfire_insn_access_exception_tl1()
223 unsigned short ctx = (type_ctx & 0xffff); in sun4v_insn_access_exception()
226 0, 0x8, SIGTRAP) == NOTIFY_STOP) in sun4v_insn_access_exception()
237 regs->tpc &= 0xffffffff; in sun4v_insn_access_exception()
238 regs->tnpc &= 0xffffffff; in sun4v_insn_access_exception()
240 force_sig_fault(SIGSEGV, SEGV_MAPERR, (void __user *) addr, 0); in sun4v_insn_access_exception()
246 0, 0x8, SIGTRAP) == NOTIFY_STOP) in sun4v_insn_access_exception_tl1()
273 if ((insn & 0xc0800000) == 0xc0800000) { /* op=3, op3[4]=1 */ in is_no_fault_exception()
274 if (insn & 0x2000) /* immediate offset */ in is_no_fault_exception()
278 if ((asi & 0xf2) == ASI_PNF) { in is_no_fault_exception()
279 if (insn & 0x1000000) { /* op3[5:4]=3 */ in is_no_fault_exception()
282 } else if (insn & 0x200000) { /* op3[2], stores */ in is_no_fault_exception()
297 0, 0x30, SIGTRAP) == NOTIFY_STOP) in spitfire_data_access_exception()
325 force_sig_fault(SIGSEGV, SEGV_MAPERR, (void __user *)sfar, 0); in spitfire_data_access_exception()
333 0, 0x30, SIGTRAP) == NOTIFY_STOP) in spitfire_data_access_exception_tl1()
343 unsigned short ctx = (type_ctx & 0xffff); in sun4v_data_access_exception()
346 0, 0x8, SIGTRAP) == NOTIFY_STOP) in sun4v_data_access_exception()
372 regs->tpc &= 0xffffffff; in sun4v_data_access_exception()
373 regs->tnpc &= 0xffffffff; in sun4v_data_access_exception()
378 /* MCD (Memory Corruption Detection) disabled trap (TT=0x19) in HV in sun4v_data_access_exception()
389 force_sig_fault(SIGILL, ILL_ILLADR, (void __user *)addr, 0); in sun4v_data_access_exception()
392 force_sig_fault(SIGSEGV, SEGV_ACCADI, (void __user *)addr, 0); in sun4v_data_access_exception()
395 force_sig_fault(SIGSEGV, SEGV_MAPERR, (void __user *)addr, 0); in sun4v_data_access_exception()
403 0, 0x8, SIGTRAP) == NOTIFY_STOP) in sun4v_data_access_exception_tl1()
423 for (va = 0; va < (PAGE_SIZE << 1); va += 32) { in spitfire_clean_and_reenable_l1_caches()
424 spitfire_put_icache_tag(va, 0x0); in spitfire_clean_and_reenable_l1_caches()
425 spitfire_put_dcache_tag(va, 0x0); in spitfire_clean_and_reenable_l1_caches()
431 "stxa %0, [%%g0] %1\n\t" in spitfire_clean_and_reenable_l1_caches()
442 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t" in spitfire_enable_estate_errors()
450 0x4c, 0x40, 0x41, 0x48, 0x42, 0x48, 0x48, 0x49,
451 0x43, 0x48, 0x48, 0x49, 0x48, 0x49, 0x49, 0x4a,
452 0x44, 0x48, 0x48, 0x20, 0x48, 0x39, 0x4b, 0x48,
453 0x48, 0x25, 0x31, 0x48, 0x28, 0x48, 0x48, 0x2c,
454 0x45, 0x48, 0x48, 0x21, 0x48, 0x3d, 0x04, 0x48,
455 0x48, 0x4b, 0x35, 0x48, 0x2d, 0x48, 0x48, 0x29,
456 0x48, 0x00, 0x01, 0x48, 0x0a, 0x48, 0x48, 0x4b,
457 0x0f, 0x48, 0x48, 0x4b, 0x48, 0x49, 0x49, 0x48,
458 0x46, 0x48, 0x48, 0x2a, 0x48, 0x3b, 0x27, 0x48,
459 0x48, 0x4b, 0x33, 0x48, 0x22, 0x48, 0x48, 0x2e,
460 0x48, 0x19, 0x1d, 0x48, 0x1b, 0x4a, 0x48, 0x4b,
461 0x1f, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
462 0x48, 0x4b, 0x24, 0x48, 0x07, 0x48, 0x48, 0x36,
463 0x4b, 0x48, 0x48, 0x3e, 0x48, 0x30, 0x38, 0x48,
464 0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x16, 0x48,
465 0x48, 0x12, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
466 0x47, 0x48, 0x48, 0x2f, 0x48, 0x3f, 0x4b, 0x48,
467 0x48, 0x06, 0x37, 0x48, 0x23, 0x48, 0x48, 0x2b,
468 0x48, 0x05, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x32,
469 0x26, 0x48, 0x48, 0x3a, 0x48, 0x34, 0x3c, 0x48,
470 0x48, 0x11, 0x15, 0x48, 0x13, 0x4a, 0x48, 0x4b,
471 0x17, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
472 0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x1e, 0x48,
473 0x48, 0x1a, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
474 0x48, 0x08, 0x0d, 0x48, 0x02, 0x48, 0x48, 0x49,
475 0x03, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x4b, 0x48,
476 0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x10, 0x48,
477 0x48, 0x14, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
478 0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x18, 0x48,
479 0x48, 0x1c, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
480 0x4a, 0x0c, 0x09, 0x48, 0x0e, 0x48, 0x48, 0x4b,
481 0x0b, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x4b, 0x4a
492 scode = ecc_syndrome_table[udbl & 0xff]; in spitfire_log_udb_syndrome()
493 if (sprintf_dimm(scode, afar, memmod_str, sizeof(memmod_str)) < 0) in spitfire_log_udb_syndrome()
503 scode = ecc_syndrome_table[udbh & 0xff]; in spitfire_log_udb_syndrome()
504 if (sprintf_dimm(scode, afar, memmod_str, sizeof(memmod_str)) < 0) in spitfire_log_udb_syndrome()
528 0, TRAP_TYPE_CEE, SIGTRAP); in spitfire_cee_log()
552 0, tt, SIGTRAP); in spitfire_ue_log()
569 regs->tpc &= 0xffffffff; in spitfire_ue_log()
570 regs->tnpc &= 0xffffffff; in spitfire_ue_log()
572 force_sig_fault(SIGBUS, BUS_OBJERR, (void *)0, 0); in spitfire_ue_log()
582 tl1 = (status_encoded & SFSTAT_TL_GT_ONE) ? 1 : 0; in spitfire_access_error()
608 "stxa %0, [%1] %2\n\t" in spitfire_access_error()
612 "r" (0x0), "i" (ASI_UDB_ERROR_W)); in spitfire_access_error()
616 "stxa %0, [%1] %2\n\t" in spitfire_access_error()
620 "r" (0x18), "i" (ASI_UDB_ERROR_W)); in spitfire_access_error()
637 __asm__ __volatile__("ldxa [%%g0] %1, %0" in cheetah_enable_pcache()
641 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t" in cheetah_enable_pcache()
720 { 0, NULL },
761 { 0, NULL },
820 { 0, NULL },
836 if ((afsr & CHAFSR_TL1) != 0UL) in cheetah_get_error_log()
863 largest_size = 0UL; in cheetah_ecache_flush_init()
864 smallest_linesize = ~0UL; in cheetah_ecache_flush_init()
866 for (i = 0; i < NR_CPUS; i++) { in cheetah_ecache_flush_init()
882 if (largest_size == 0UL || smallest_linesize == ~0UL) { in cheetah_ecache_flush_init()
893 if (ecache_flush_physbase == ~0UL) { in cheetah_ecache_flush_init()
902 for (order = 0; order < MAX_ORDER; order++) { in cheetah_ecache_flush_init()
913 memset(cheetah_error_log, 0, PAGE_SIZE << order); in cheetah_ecache_flush_init()
918 for (i = 0; i < 2 * NR_CPUS; i++) in cheetah_ecache_flush_init()
921 __asm__ ("rdpr %%ver, %0" : "=r" (ver)); in cheetah_ecache_flush_init()
924 cheetah_error_table = &__jalapeno_error_table[0]; in cheetah_ecache_flush_init()
926 } else if ((ver >> 32) == 0x003e0015) { in cheetah_ecache_flush_init()
927 cheetah_error_table = &__cheetah_plus_error_table[0]; in cheetah_ecache_flush_init()
930 cheetah_error_table = &__cheetah_error_table[0]; in cheetah_ecache_flush_init()
958 __asm__ __volatile__("1: subcc %0, %4, %0\n\t" in cheetah_flush_ecache()
960 " ldxa [%2 + %0] %3, %%g0\n\t" in cheetah_flush_ecache()
962 : "0" (flush_size), "r" (flush_base), in cheetah_flush_ecache()
974 __asm__ __volatile__("ldxa [%0] %2, %%g0\n\t" in cheetah_flush_ecache_line()
996 for (addr = 0; addr < icache_size; addr += icache_line_size) { in __cheetah_flush_icache()
997 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" in __cheetah_flush_icache()
1010 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t" in cheetah_flush_icache()
1011 "or %0, %2, %%g1\n\t" in cheetah_flush_icache()
1021 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t" in cheetah_flush_icache()
1035 for (addr = 0; addr < dcache_size; addr += dcache_line_size) { in cheetah_flush_dcache()
1036 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" in cheetah_flush_dcache()
1056 for (addr = 0; addr < dcache_size; addr += dcache_line_size) { in cheetah_plus_zap_dcache_parity()
1061 "stxa %0, [%1] %2\n\t" in cheetah_plus_zap_dcache_parity()
1068 "stxa %%g0, [%0] %1\n\t" in cheetah_plus_zap_dcache_parity()
1105 /*03*/M2, 40, 13, M2, 59, M, M2, 66, M, M2, M2, 0, M2, 67, 71, M,
1112 /*0a*/M2, 23, 113, M2, 112, M2, M, 51, 95, M, M2, M3, M2, M3, M3, M2,
1113 /*0b*/103, M, M2, M3, M2, M3, M3, M4, M2, 48, M, M, 73, M2, M, M3,
1114 /*0c*/M2, 22, 110, M2, 109, M2, M, 9, 108, M2, M, M3, M2, M3, M3, M,
1115 /*0d*/102, M2, M, M, M2, M3, M3, M, M2, M3, M3, M2, M, M4, M, M3,
1116 /*0e*/98, M, M2, M3, M2, M, M3, M4, M2, M3, M3, M4, M3, M, M, M,
1117 /*0f*/M2, M3, M3, M, M3, M, M, M, 56, M4, M, M3, M4, M, M, M,
1149 unsigned long tmp = 0; in cheetah_get_hipri()
1152 for (i = 0; cheetah_error_table[i].mask; i++) { in cheetah_get_hipri()
1153 if ((tmp = (afsr & cheetah_error_table[i].mask)) != 0UL) in cheetah_get_hipri()
1163 for (i = 0; cheetah_error_table[i].mask; i++) { in cheetah_get_string()
1164 if ((bit & cheetah_error_table[i].mask) != 0UL) in cheetah_get_string()
1179 (afsr & CHAFSR_TL1) ? 1 : 0); in cheetah_log_errors()
1238 info->dcache_data[0], in cheetah_log_errors()
1253 info->icache_data[0], in cheetah_log_errors()
1268 info->ecache_data[0], in cheetah_log_errors()
1274 while (afsr != 0UL) { in cheetah_log_errors()
1291 int ret = 0; in cheetah_recheck_errors()
1293 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t" in cheetah_recheck_errors()
1296 if ((afsr & cheetah_afsr_errors) != 0) { in cheetah_recheck_errors()
1298 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t" in cheetah_recheck_errors()
1306 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t" in cheetah_recheck_errors()
1349 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t" in cheetah_fecc_handler()
1351 "stxa %%g1, [%%g0] %0\n\t" in cheetah_fecc_handler()
1359 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t" in cheetah_fecc_handler()
1361 "stxa %%g1, [%%g0] %0\n\t" in cheetah_fecc_handler()
1373 recoverable = 0; in cheetah_fecc_handler()
1386 recoverable = 0; in cheetah_fecc_handler()
1410 __asm__ __volatile__("ldxa [%%g0] %2, %0\n\t" in cheetah_fix_ce()
1411 "andn %0, %1, %%g1\n\t" in cheetah_fix_ce()
1430 __asm__ __volatile__("ldxa [%0] %3, %%g0\n\t" in cheetah_fix_ce()
1433 "ldxa [%0] %3, %%g0\n\t" in cheetah_fix_ce()
1443 __asm__ __volatile__("ldxa [%0] %1, %%g0\n\t" in cheetah_fix_ce()
1452 ret = 0; in cheetah_fix_ce()
1456 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t" in cheetah_fix_ce()
1469 return 0; in cheetah_check_main_memory()
1505 if (is_memory && (afsr & CHAFSR_CE) != 0UL) { in cheetah_cee_handler()
1515 flush_all = flush_line = 0; in cheetah_cee_handler()
1516 if ((afsr & CHAFSR_EDC) != 0UL) { in cheetah_cee_handler()
1521 } else if ((afsr & CHAFSR_CPC) != 0UL) { in cheetah_cee_handler()
1532 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t" in cheetah_cee_handler()
1534 "stxa %%g1, [%%g0] %0\n\t" in cheetah_cee_handler()
1548 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t" in cheetah_cee_handler()
1550 "stxa %%g1, [%%g0] %0\n\t" in cheetah_cee_handler()
1562 recoverable = 0; in cheetah_cee_handler()
1586 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t" in cheetah_deferred_handler()
1588 "stxa %%g1, [%%g0] %0\n\t" in cheetah_deferred_handler()
1596 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t" in cheetah_deferred_handler()
1598 "stxa %%g1, [%%g0] %0\n\t" in cheetah_deferred_handler()
1643 flush_all = flush_line = 0; in cheetah_deferred_handler()
1644 if ((afsr & CHAFSR_EDU) != 0UL) { in cheetah_deferred_handler()
1649 } else if ((afsr & CHAFSR_BERR) != 0UL) { in cheetah_deferred_handler()
1660 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t" in cheetah_deferred_handler()
1662 "stxa %%g1, [%%g0] %0\n\t" in cheetah_deferred_handler()
1676 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t" in cheetah_deferred_handler()
1678 "stxa %%g1, [%%g0] %0\n\t" in cheetah_deferred_handler()
1690 recoverable = 0; in cheetah_deferred_handler()
1703 recoverable = 0; in cheetah_deferred_handler()
1722 if ((regs->tstate & TSTATE_PRIV) == 0UL) { in cheetah_deferred_handler()
1735 recoverable = 0; in cheetah_deferred_handler()
1742 recoverable = 0; in cheetah_deferred_handler()
1754 recoverable = 0; in cheetah_deferred_handler()
1763 * Bit0: 0=dcache,1=icache
1764 * Bit1: 0=recoverable,1=unrecoverable
1771 if (type & 0x1) in cheetah_plus_parity_error()
1778 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t" in cheetah_plus_parity_error()
1780 "stxa %%g1, [%%g0] %0\n\t" in cheetah_plus_parity_error()
1787 if (type & 0x2) { in cheetah_plus_parity_error()
1790 (type & 0x1) ? 'I' : 'D', in cheetah_plus_parity_error()
1798 (type & 0x1) ? 'I' : 'D', in cheetah_plus_parity_error()
1805 /*0x00*/u64 err_handle;
1808 /*0x08*/u64 err_stick;
1810 /*0x10*/u8 reserved_1[3];
1813 /*0x13*/u8 err_type;
1814 #define SUN4V_ERR_TYPE_UNDEFINED 0
1824 /*0x14*/u32 err_attrs;
1825 #define SUN4V_ERR_ATTRS_PROCESSOR 0x00000001
1826 #define SUN4V_ERR_ATTRS_MEMORY 0x00000002
1827 #define SUN4V_ERR_ATTRS_PIO 0x00000004
1828 #define SUN4V_ERR_ATTRS_INT_REGISTERS 0x00000008
1829 #define SUN4V_ERR_ATTRS_FPU_REGISTERS 0x00000010
1830 #define SUN4V_ERR_ATTRS_SHUTDOWN_RQST 0x00000020
1831 #define SUN4V_ERR_ATTRS_ASR 0x00000040
1832 #define SUN4V_ERR_ATTRS_ASI 0x00000080
1833 #define SUN4V_ERR_ATTRS_PRIV_REG 0x00000100
1834 #define SUN4V_ERR_ATTRS_SPSTATE_MSK 0x00000600
1835 #define SUN4V_ERR_ATTRS_MCD 0x00000800
1837 #define SUN4V_ERR_ATTRS_MODE_MSK 0x03000000
1839 #define SUN4V_ERR_ATTRS_RES_QUEUE_FULL 0x80000000
1841 #define SUN4V_ERR_SPSTATE_FAULTED 0
1849 /*0x18*/u64 err_raddr;
1852 /*0x20*/u32 err_size;
1855 /*0x24*/u16 err_cpu;
1858 /*0x26*/u16 err_secs;
1861 /*0x28*/u8 err_asi;
1863 /*0x29*/u8 reserved_2;
1866 /*0x2a*/u16 err_asr;
1867 #define SUN4V_ERR_ASR_VALID 0x8000
1869 /*0x2c*/u32 reserved_3;
1870 /*0x30*/u64 reserved_4;
1871 /*0x38*/u64 reserved_5;
1874 static atomic_t sun4v_resum_oflow_cnt = ATOMIC_INIT(0);
1875 static atomic_t sun4v_nonresum_oflow_cnt = ATOMIC_INIT(0);
1923 for (i = 0; i < ARRAY_SIZE(attr_names); i++) { in sun4v_emit_err_attr_strings()
1960 addr = compute_effective_address(regs, insn, 0); in sun4v_report_real_raddr()
1962 printk("%s: insn effective address [0x%016llx]\n", in sun4v_report_real_raddr()
1974 printk("%s: TPC [0x%016lx] <%pS>\n", in sun4v_log_error()
1978 pfx, raw_ptr[0], raw_ptr[1], raw_ptr[2], raw_ptr[3]); in sun4v_log_error()
1982 printk("%s: handle [0x%016llx] stick [0x%016llx]\n", in sun4v_log_error()
1988 printk("%s: attrs [0x%08x] < ", pfx, attrs); in sun4v_log_error()
1998 printk("%s: raddr [0x%016llx]\n", pfx, ent->err_raddr); in sun4v_log_error()
2000 if (ent->err_raddr == ~(u64)0) in sun4v_log_error()
2005 printk("%s: size [0x%x]\n", pfx, ent->err_size); in sun4v_log_error()
2014 printk("%s: asi [0x%02x]\n", pfx, ent->err_asi); in sun4v_log_error()
2019 (ent->err_asr & SUN4V_ERR_ASR_VALID) != 0) in sun4v_log_error()
2020 printk("%s: reg [0x%04x]\n", in sun4v_log_error()
2025 if ((cnt = atomic_read(ocnt)) != 0) { in sun4v_log_error()
2026 atomic_set(ocnt, 0); in sun4v_log_error()
2038 if (notify_die(DIE_TRAP, "MCD error", regs, 0, 0x34, in do_mcd_err()
2074 0); in do_mcd_err()
2097 ent->err_handle = 0; in sun4v_resum_error()
2147 (insn >> 25) & 0x1f); in sun4v_get_vaddr()
2149 return 0; in sun4v_get_vaddr()
2163 if (addr == ~(u64)0) { in sun4v_nonresum_error_user_handled()
2176 while (page_cnt-- > 0) { in sun4v_nonresum_error_user_handled()
2188 (void __user *)sun4v_get_vaddr(regs), 0); in sun4v_nonresum_error_user_handled()
2215 ent->err_handle = 0; in sun4v_nonresum_error()
2324 unsigned long fsr = current_thread_info()->xfsr[0]; in do_fpe_common()
2328 regs->tpc &= 0xffffffff; in do_fpe_common()
2329 regs->tnpc &= 0xffffffff; in do_fpe_common()
2332 if ((fsr & 0x1c000) == (1 << 14)) { in do_fpe_common()
2333 if (fsr & 0x10) in do_fpe_common()
2335 else if (fsr & 0x08) in do_fpe_common()
2337 else if (fsr & 0x04) in do_fpe_common()
2339 else if (fsr & 0x02) in do_fpe_common()
2341 else if (fsr & 0x01) in do_fpe_common()
2345 (void __user *)regs->tpc, 0); in do_fpe_common()
2354 0, 0x24, SIGFPE) == NOTIFY_STOP) in do_fpieee()
2366 int ret = 0; in do_fpother()
2369 0, 0x25, SIGFPE) == NOTIFY_STOP) in do_fpother()
2372 switch ((current_thread_info()->xfsr[0] & 0x1c000)) { in do_fpother()
2390 0, 0x26, SIGEMT) == NOTIFY_STOP) in do_tof()
2396 regs->tpc &= 0xffffffff; in do_tof()
2397 regs->tnpc &= 0xffffffff; in do_tof()
2400 (void __user *)regs->tpc, 0); in do_tof()
2410 0, 0x28, SIGFPE) == NOTIFY_STOP) in do_div0()
2416 regs->tpc &= 0xffffffff; in do_div0()
2417 regs->tnpc &= 0xffffffff; in do_div0()
2420 (void __user *)regs->tpc, 0); in do_div0()
2450 for (i = 0; i < 9; i++) in user_instruction_dump()
2459 int count = 0; in show_stack()
2461 int graph = 0; in show_stack()
2468 if (ksp == 0UL) { in show_stack()
2470 asm("mov %%fp, %0" : "=r" (ksp)); in show_stack()
2528 int count = 0; in die_if_kernel()
2538 notify_die(DIE_OOPS, str, regs, 0, 255, SIGSEGV); in die_if_kernel()
2561 regs->tpc &= 0xffffffff; in die_if_kernel()
2562 regs->tnpc &= 0xffffffff; in die_if_kernel()
2574 #define VIS_OPCODE_MASK ((0x3 << 30) | (0x3f << 19))
2575 #define VIS_OPCODE_VAL ((0x2 << 30) | (0x36 << 19))
2585 0, 0x10, SIGILL) == NOTIFY_STOP) in do_illegal_instruction()
2593 if ((insn & 0xc1ffc000) == 0x81700000) /* POPC */ { in do_illegal_instruction()
2596 } else if ((insn & 0xc1580000) == 0xc1100000) /* LDQ/STQ */ { in do_illegal_instruction()
2616 force_sig_fault(SIGILL, ILL_ILLOPC, (void __user *)pc, 0); in do_illegal_instruction()
2626 0, 0x34, SIGSEGV) == NOTIFY_STOP) in mem_address_unaligned()
2636 force_sig_fault(SIGBUS, BUS_ADRALN, (void __user *)sfar, 0); in mem_address_unaligned()
2644 0, 0x34, SIGSEGV) == NOTIFY_STOP) in sun4v_do_mna()
2654 force_sig_fault(SIGBUS, BUS_ADRALN, (void __user *) addr, 0); in sun4v_do_mna()
2668 0, 0x8, SIGSEGV) == NOTIFY_STOP) in sun4v_mem_corrupt_detect_precise()
2698 regs->tpc &= 0xffffffff; in sun4v_mem_corrupt_detect_precise()
2699 regs->tnpc &= 0xffffffff; in sun4v_mem_corrupt_detect_precise()
2701 force_sig_fault(SIGSEGV, SEGV_ADIPERR, (void __user *)addr, 0); in sun4v_mem_corrupt_detect_precise()
2709 0, 0x11, SIGILL) == NOTIFY_STOP) in do_privop()
2713 regs->tpc &= 0xffffffff; in do_privop()
2714 regs->tnpc &= 0xffffffff; in do_privop()
2717 (void __user *)regs->tpc, 0); in do_privop()
2822 regs->tpc &= 0xffffffff; in do_getpsr()
2823 regs->tnpc &= 0xffffffff; in do_getpsr()
2827 u64 cpu_mondo_counter[NR_CPUS] = {0};
2840 p->pgd_paddr = 0; in init_cur_cpu_trap()