Lines Matching +full:0 +full:x600

19  *  31    24 23-21 20-19 18 17 16-15 14 13-10  9  8  7  6-3   2  1  0
21 * BM: Boot Mode -- 0 = not in boot mode, 1 = in boot mode
25 * IC: Instruction Cache -- 0 = off, 1 = on
26 * DC: Data Cache -- 0 = off, 1 = 0n
30 * ICS: ICache Snooping -- 0 = disable, 1 = enable snooping of icache
31 * NF: No Fault -- 0 = faults generate traps, 1 = faults don't trap
32 * ME: MMU enable -- 0 = mmu not translating, 1 = mmu translating
36 #define TURBOSPARC_MMUENABLE 0x00000001
37 #define TURBOSPARC_NOFAULT 0x00000002
38 #define TURBOSPARC_ICSNOOP 0x00000004
39 #define TURBOSPARC_PSO 0x00000080
40 #define TURBOSPARC_DCENABLE 0x00000100 /* Enable data cache */
41 #define TURBOSPARC_ICENABLE 0x00000200 /* Enable instruction cache */
42 #define TURBOSPARC_BMODE 0x00004000
43 #define TURBOSPARC_PARITYODD 0x00020000 /* Parity odd, if enabled */
44 #define TURBOSPARC_PCENABLE 0x00040000 /* Enable parity checking */
51 * 31 30 29-28 27-26 25-23 22-8 7-6 5 4 3 2-0
55 #define TURBOSPARC_SCENABLE 0x00000008 /* Secondary cache enable */
56 #define TURBOSPARC_uS2 0x00000010 /* Swift compatibility mode */
57 #define TURBOSPARC_WTENABLE 0x00000020 /* Write thru for dcache */
58 #define TURBOSPARC_SNENABLE 0x40000000 /* DVMA snoop enable */
65 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" in turbosparc_inv_insn_tag()
74 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" in turbosparc_inv_data_tag()
84 for (addr = 0; addr < 0x4000; addr += 0x20) in turbosparc_flush_icache()
92 for (addr = 0; addr < 0x4000; addr += 0x20) in turbosparc_flush_dcache()
100 for (addr = 0; addr < 0x4000; addr += 0x20) { in turbosparc_idflash_clear()
108 __asm__ __volatile__("sta %0, [%1] %2\n\t" in turbosparc_set_ccreg()
110 : "r" (regval), "r" (0x600), "i" (ASI_M_MMUREGS) in turbosparc_set_ccreg()
118 __asm__ __volatile__("lda [%1] %2, %0\n\t" in turbosparc_get_ccreg()
120 : "r" (0x600), "i" (ASI_M_MMUREGS)); in turbosparc_get_ccreg()