include/asm/tsb.h

1 /* SPDX-License-Identifier: GPL-2.0 */
6  * power-of-2 sized table of TAG/PTE pairs.  The cpu precomputes
11  * TLB miss trap handler software does the actual lookup via something
14  * 	ldxa		[%g0] ASI_{D,I}MMU_TSB_8KB_PTR, %g1
15  * 	ldxa		[%g0] ASI_{D,I}MMU, %g6
20  * 	bne,pn	%xcc, tsb_miss_{d,i}tlb
21  * 	 mov		FAULT_CODE_{D,I}TLB, %g3
22  * 	stxa		%g5, [%g0] ASI_{D,I}TLB_DATA_IN
26  * Each 16-byte slot of the TSB is the 8-byte tag and then the 8-byte
27  * PTE.  The TAG is of the same layout as the TLB TAG TARGET mmu
30  * -------------------------------------------------
31  * |  -  |  CONTEXT |  -  |    VADDR bits 63:22    |
32  * -------------------------------------------------
35  * But actually, since we use per-mm TSB's, we zero out the CONTEXT
49 #define TSB_TAG_LOCK_HIGH	(1 << (TSB_TAG_LOCK_BIT - 32))
52 #define TSB_TAG_INVALID_HIGH	(1 << (TSB_TAG_INVALID_BIT - 32))
55  * those if possible so we don't need to hard-lock the TSB mapping
56  * into the TLB.  We encode some instruction patching in order to
59  * The kernel TSB is locked into the TLB by virtue of being in the
144 	 * table boundaries do not match the huge page size(s) the
150 	 * page size in question.  So for PMD mappings (which fall on
159 	sllx		VADDR, 64 - (PGDIR_SHIFT + PGDIR_BITS), REG2; \
160 	srlx		REG2, 64 - PAGE_SHIFT, REG2; \
164 	 sllx		VADDR, 64 - (PUD_SHIFT + PUD_BITS), REG2; \
165 	srlx		REG2, 64 - PAGE_SHIFT, REG2; \
176 	sllx		VADDR, 64 - (PMD_SHIFT + PMD_BITS), REG2; \
177 	srlx		REG2, 64 - PAGE_SHIFT, REG2; \
191 698:	sllx		VADDR, 64 - PMD_SHIFT, REG2; \
192 	srlx		REG2, 64 - PAGE_SHIFT, REG2; \
272 	sllx		VADDR, 64 - (PGDIR_SHIFT + PGDIR_BITS), REG2; \
273 	srlx		REG2, 64 - PAGE_SHIFT, REG2; \
277 	 sllx		VADDR, 64 - (PUD_SHIFT + PUD_BITS), REG2; \
278 	srlx		REG2, 64 - PAGE_SHIFT, REG2; \
283 	 sllx		VADDR, 64 - (PMD_SHIFT + PMD_BITS), REG2; \
284 	srlx		REG2, 64 - PAGE_SHIFT, REG2; \
288 	sllx		VADDR, 64 - PMD_SHIFT, REG2; \
289 	srlx		REG2, 64 - PAGE_SHIFT, REG2; \
349 	and		REG2, (KERNEL_TSB_NENTRIES - 1), REG2; \
371 	and		TAG, (KERNEL_TSB4M_NENTRIES - 1), REG2; \