Lines Matching +full:0 +full:x08000000
16 #define PHYS_EMI_CBLOCK P4SEGADDR(0x1ec00000)
17 #define PHYS_EMI_DBLOCK P4SEGADDR(0x08000000)
18 #define PHYS_FEMI_CBLOCK P4SEGADDR(0x1f800000)
19 #define PHYS_FEMI_DBLOCK P4SEGADDR(0x00000000)
21 #define PHYS_EPBR_BLOCK P4SEGADDR(0x1de00000)
22 #define PHYS_DMAC_BLOCK P4SEGADDR(0x1fa00000)
23 #define PHYS_PBR_BLOCK P4SEGADDR(0x1fc00000)
26 [0] = {
28 .end = PHYS_EMI_CBLOCK + 0x00300000 - 1,
33 .end = PHYS_EMI_DBLOCK + 0x08000000 - 1,
45 [0] = {
47 .end = PHYS_FEMI_CBLOCK + 0x00100000 - 1,
52 .end = PHYS_FEMI_DBLOCK + 0x08000000 - 1,
64 [0] = {
65 .start = P4SEGADDR(0x1e7ffff8),
66 .end = P4SEGADDR(0x1e7ffff8 + (sizeof(u32) * 2) - 1),
71 .end = PHYS_EPBR_BLOCK + 0x00a00000 - 1,
84 .end = PHYS_DMAC_BLOCK + 0x00100000 - 1,
95 [0] = {
96 .start = P4SEGADDR(0x1ffffff8),
97 .end = P4SEGADDR(0x1ffffff8 + (sizeof(u32) * 2) - 1),
102 .end = PHYS_PBR_BLOCK + 0x00400000 - (sizeof(u32) * 2) - 1,
124 * indicates that VCRL is mapped first with VCRH at a + 0x04 in sh4202_read_vcr()
140 return 0; in sh4202_read_vcr()
147 __raw_writel((tmp >> 32) & 0xffffffff, base); in sh4202_write_vcr()
148 __raw_writel(tmp & 0xffffffff, base + sizeof(u32)); in sh4202_write_vcr()
150 return 0; in sh4202_write_vcr()
160 { 0, },