Lines Matching +full:0 +full:x11000

13 #define EP_OFFSET		0x10008
15 #define PARMAREA		0x10400
16 #define EARLY_SCCB_OFFSET	0x11000
17 #define HEAD_END		0x12000
25 #define MACHINE_FLAG_VM		BIT(0)
43 #define LPP_PID_MASK		_AC(0xffffffff, UL)
47 #define STARTUP_NORMAL_OFFSET	0x10000
48 #define STARTUP_KDUMP_OFFSET	0x10010
52 #define IPL_DEVICE_OFFSET	0x10400
53 #define INITRD_START_OFFSET	0x10408
54 #define INITRD_SIZE_OFFSET	0x10410
55 #define OLDMEM_BASE_OFFSET	0x10418
56 #define OLDMEM_SIZE_OFFSET	0x10420
57 #define KERNEL_VERSION_OFFSET	0x10428
58 #define COMMAND_LINE_OFFSET	0x10480
73 	unsigned long ipl_device;			/* 0x10400 */
74 	unsigned long initrd_start;			/* 0x10408 */
75 	unsigned long initrd_size;			/* 0x10410 */
76 	unsigned long oldmem_base;			/* 0x10418 */
77 	unsigned long oldmem_size;			/* 0x10420 */
78 	unsigned long kernel_version;			/* 0x10428 */
79 	char pad1[0x10480 - 0x10430];			/* 0x10430 - 0x10480 */
80 	char command_line[ARCH_COMMAND_LINE_SIZE];	/* 0x10480 */
84 #define ZLIB_DFLTCC_DISABLED		0
124 #define CONSOLE_IS_UNDEFINED	(console_mode == 0)
130 #define SET_CONSOLE_SCLP	do { console_mode = 1; } while (0)
131 #define SET_CONSOLE_3215	do { console_mode = 2; } while (0)
132 #define SET_CONSOLE_3270	do { console_mode = 3; } while (0)
133 #define SET_CONSOLE_VT220	do { console_mode = 4; } while (0)
134 #define SET_CONSOLE_HVC		do { console_mode = 5; } while (0)
141 #define pfault_fini()		do { } while (0)
167 	BUILD_BUG_ON(addr > 0xfff);  in gen_lpswe()
168 	return 0xb2b20000 | addr;  in gen_lpswe()