include/asm/pgtable.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
12 #include <asm/pgtable-bits.h>
16 /* Page Upper Directory not used in RISC-V */
17 #include <asm-generic/pgtable-nopud.h>
25 #define VMALLOC_END      (PAGE_OFFSET - 1)
26 #define VMALLOC_START    (PAGE_OFFSET - VMALLOC_SIZE)
29 #define BPF_JIT_REGION_START	(PAGE_OFFSET - BPF_JIT_REGION_SIZE)
38 	(CONFIG_VA_BITS - PAGE_SHIFT - 1 + STRUCT_PAGE_MAX_SHIFT)
40 #define VMEMMAP_END	(VMALLOC_START - 1)
41 #define VMEMMAP_START	(VMALLOC_START - VMEMMAP_SIZE)
51 #define PCI_IO_START     (PCI_IO_END - PCI_IO_SIZE)
59 #define FIXADDR_START    (FIXADDR_TOP - FIXADDR_SIZE)
64 #include <asm/pgtable-64.h>
66 #include <asm/pgtable-32.h>
75 /* Number of PGD entries that a user-mode program can use */
111  * The RISC-V ISA doesn't yet specify how to query or modify PMAs, so we can't
118 /* MAP_PRIVATE permissions: xwr (copy-on-write) */
309 	 * in RISC-V, SFENCE.VMA specifies an ordering constraint, not a  in update_mmu_cache()
356 		set_pte_at(vma->vm_mm, address, ptep, entry);  in ptep_set_access_flags()
393 	 * This comment is borrowed from x86, but applies equally to RISC-V:  in ptep_clear_flush_young()
417  *	bits 7 to XLEN-1:	swap offset
421 #define __SWP_TYPE_MASK		((1UL << __SWP_TYPE_BITS) - 1)
436  * In the RV64 Linux scheme, we give the user half of the virtual-address space
440 #define KERN_VIRT_START	(-(BIT(CONFIG_VA_BITS)) + TASK_SIZE)
479  * used for zero-mapped memory areas, etc.