dts/sifive/hifive-unleashed-a00.dts

1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 #include "fu540-c000.dtsi"
5 #include <dt-bindings/gpio/gpio.h>
7 /* Clock frequency (in Hz) of the PCB crystal for rtcclk */
11 	#address-cells = <2>;
12 	#size-cells = <2>;
14 	compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000";
17 		stdout-path = "serial0";
21 		timebase-frequency = <RTCCLK_FREQ>;
33 		#clock-cells = <0>;
34 		compatible = "fixed-clock";
35 		clock-frequency = <33333333>;
36 		clock-output-names = "hfclk";
40 		#clock-cells = <0>;
41 		compatible = "fixed-clock";
42 		clock-frequency = <RTCCLK_FREQ>;
43 		clock-output-names = "rtcclk";
45 	gpio-restart {
46 		compatible = "gpio-restart";
66 		compatible = "issi,is25wp256", "jedec,spi-nor";
68 		spi-max-frequency = <50000000>;
69 		m25p,fast-read;
70 		spi-tx-bus-width = <4>;
71 		spi-rx-bus-width = <4>;
78 		compatible = "mmc-spi-slot";
80 		spi-max-frequency = <20000000>;
81 		voltage-ranges = <3300 3300>;
82 		disable-wp;
88 	phy-mode = "gmii";
89 	phy-handle = <&phy0>;
90 	phy0: ethernet-phy@0 {