powerpc/xmon/ppc.h

1 /* ppc.h -- Header file for PowerPC opcode table
2    Copyright (C) 1994-2016 Free Software Foundation, Inc.
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
88    (ie, compiler's -mcpu=common or assembler's -mcom).  More than just
95    for the assembler's -many option, and it eliminates duplicates).  */
101 /* Opcode is supported as part of the 64-bit bridge.  */
164 /* Opcode is supported by Vector-Scalar (VSX) Unit */
211 /* Opcode is supported by Vector-Scalar (VSX) Unit from ISA 2.08.  */
220 /* A macro to determine if the instruction is a 2-byte VLE insn.  */
239      is shifted right by -SHIFT.  Use PPC_OPSHIFT_INV to indicate
248 	 if (o->shift >= 0)
249 	   i |= (op & o->bitm) << o->shift;
251 	   i |= (op & o->bitm) >> -o->shift;
269 	 if (o->shift >= 0)
270 	   op = (i >> o->shift) & o->bitm;
272 	   op = (i << -o->shift) & o->bitm;
273 	 if ((o->flags & PPC_OPERAND_SIGNED) != 0)
281      non-zero if this operand type can not actually be extracted from
299 #define PPC_OPSHIFT_INV (-1U << 31)
308    16, it takes any value from -0x8000 to 0xffff.  In 64 bit mode,
323        reg,displacement(reg)
327 /* This operand may use the symbolic names for the CR fields, which
336 /* This operand names a register.  The disassembler uses this to print
337    register names with a leading 'r'.  */
343 /* This operand names a floating point register.  The disassembler
378 /* This operand names a vector unit register.  The disassembler
388 /* Valid range of operand is 0..n rather than 0..n-1.  */
396 /* This operand names a vector-scalar unit register.  The disassembler
400 /* This is a CR FIELD that does not use symbolic names.  */
409    only optional when generating 32-bit code.  */
443   if ((operand->flags & PPC_OPERAND_OPTIONAL_VALUE) != 0)  in ppc_optional_operand_value()
444     return (operand+1)->shift;  in ppc_optional_operand_value()