Lines Matching +full:reserved +full:- +full:ipi +full:- +full:vectors
9 * Copyright 2010-2012 Freescale Semiconductor, Inc.
150 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
162 if (!(mpic->flags & MPIC_SECONDARY)) in mpic_processor_id()
180 return dcr_read(rb->dhost, reg); in _mpic_read()
183 return in_be32(rb->base + (reg >> 2)); in _mpic_read()
186 return in_le32(rb->base + (reg >> 2)); in _mpic_read()
197 dcr_write(rb->dhost, reg, value); in _mpic_write()
201 out_be32(rb->base + (reg >> 2), value); in _mpic_write()
205 out_le32(rb->base + (reg >> 2), value); in _mpic_write()
210 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi) in _mpic_ipi_read() argument
212 enum mpic_reg_type type = mpic->reg_type; in _mpic_ipi_read()
214 (ipi * MPIC_INFO(GREG_IPI_STRIDE)); in _mpic_ipi_read()
216 if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le) in _mpic_ipi_read()
218 return _mpic_read(type, &mpic->gregs, offset); in _mpic_ipi_read()
221 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value) in _mpic_ipi_write() argument
224 (ipi * MPIC_INFO(GREG_IPI_STRIDE)); in _mpic_ipi_write()
226 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value); in _mpic_ipi_write()
240 return _mpic_read(mpic->reg_type, &mpic->tmregs, offset); in _mpic_tm_read()
248 _mpic_write(mpic->reg_type, &mpic->tmregs, offset, value); in _mpic_tm_write()
255 return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg); in _mpic_cpu_read()
262 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value); in _mpic_cpu_write()
267 unsigned int isu = src_no >> mpic->isu_shift; in _mpic_irq_read()
268 unsigned int idx = src_no & mpic->isu_mask; in _mpic_irq_read()
271 val = _mpic_read(mpic->reg_type, &mpic->isus[isu], in _mpic_irq_read()
276 mpic->isu_reg0_shadow[src_no]; in _mpic_irq_read()
284 unsigned int isu = src_no >> mpic->isu_shift; in _mpic_irq_write()
285 unsigned int idx = src_no & mpic->isu_mask; in _mpic_irq_write()
287 _mpic_write(mpic->reg_type, &mpic->isus[isu], in _mpic_irq_write()
292 mpic->isu_reg0_shadow[src_no] = in _mpic_irq_write()
297 #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r))
298 #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))
318 rb->base = ioremap(phys_addr + offset, size); in _mpic_map_mmio()
319 BUG_ON(rb->base == NULL); in _mpic_map_mmio()
326 phys_addr_t phys_addr = dcr_resource_start(mpic->node, 0); in _mpic_map_dcr()
327 rb->dhost = dcr_map(mpic->node, phys_addr + offset, size); in _mpic_map_dcr()
328 BUG_ON(!DCR_MAP_OK(rb->dhost)); in _mpic_map_dcr()
335 if (mpic->flags & MPIC_USES_DCR) in mpic_map()
347 * reads from IPI registers
353 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK); in mpic_test_broken_ipi()
354 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0)); in mpic_test_broken_ipi()
357 printk(KERN_INFO "mpic: Detected reversed IPI registers\n"); in mpic_test_broken_ipi()
358 mpic->flags |= MPIC_BROKEN_IPI; in mpic_test_broken_ipi()
369 if (source >= 128 || !mpic->fixups) in mpic_is_ht_interrupt()
371 return mpic->fixups[source].base != NULL; in mpic_is_ht_interrupt()
377 struct mpic_irq_fixup *fixup = &mpic->fixups[source]; in mpic_ht_end_irq()
379 if (fixup->applebase) { in mpic_ht_end_irq()
380 unsigned int soff = (fixup->index >> 3) & ~3; in mpic_ht_end_irq()
381 unsigned int mask = 1U << (fixup->index & 0x1f); in mpic_ht_end_irq()
382 writel(mask, fixup->applebase + soff); in mpic_ht_end_irq()
384 raw_spin_lock(&mpic->fixup_lock); in mpic_ht_end_irq()
385 writeb(0x11 + 2 * fixup->index, fixup->base + 2); in mpic_ht_end_irq()
386 writel(fixup->data, fixup->base + 4); in mpic_ht_end_irq()
387 raw_spin_unlock(&mpic->fixup_lock); in mpic_ht_end_irq()
394 struct mpic_irq_fixup *fixup = &mpic->fixups[source]; in mpic_startup_ht_interrupt()
398 if (fixup->base == NULL) in mpic_startup_ht_interrupt()
402 source, fixup->index); in mpic_startup_ht_interrupt()
403 raw_spin_lock_irqsave(&mpic->fixup_lock, flags); in mpic_startup_ht_interrupt()
405 writeb(0x10 + 2 * fixup->index, fixup->base + 2); in mpic_startup_ht_interrupt()
406 tmp = readl(fixup->base + 4); in mpic_startup_ht_interrupt()
410 writel(tmp, fixup->base + 4); in mpic_startup_ht_interrupt()
411 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags); in mpic_startup_ht_interrupt()
416 mpic->save_data[source].fixup_data = tmp | 1; in mpic_startup_ht_interrupt()
422 struct mpic_irq_fixup *fixup = &mpic->fixups[source]; in mpic_shutdown_ht_interrupt()
426 if (fixup->base == NULL) in mpic_shutdown_ht_interrupt()
432 raw_spin_lock_irqsave(&mpic->fixup_lock, flags); in mpic_shutdown_ht_interrupt()
433 writeb(0x10 + 2 * fixup->index, fixup->base + 2); in mpic_shutdown_ht_interrupt()
434 tmp = readl(fixup->base + 4); in mpic_shutdown_ht_interrupt()
436 writel(tmp, fixup->base + 4); in mpic_shutdown_ht_interrupt()
437 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags); in mpic_shutdown_ht_interrupt()
442 mpic->save_data[source].fixup_data = tmp & ~1; in mpic_shutdown_ht_interrupt()
475 printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n", in mpic_scan_ht_msi()
514 printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x" in mpic_scan_ht_pic()
526 mpic->fixups[irq].index = i; in mpic_scan_ht_pic()
527 mpic->fixups[irq].base = base; in mpic_scan_ht_pic()
528 /* Apple HT PIC has a non-standard way of doing EOIs */ in mpic_scan_ht_pic()
530 mpic->fixups[irq].applebase = devbase + 0x60; in mpic_scan_ht_pic()
532 mpic->fixups[irq].applebase = NULL; in mpic_scan_ht_pic()
534 mpic->fixups[irq].data = readl(base + 4) | 0x80000000; in mpic_scan_ht_pic()
547 mpic->fixups = kcalloc(128, sizeof(*mpic->fixups), GFP_KERNEL); in mpic_scan_ht_pics()
548 BUG_ON(mpic->fixups == NULL); in mpic_scan_ht_pics()
551 raw_spin_lock_init(&mpic->fixup_lock); in mpic_scan_ht_pics()
553 /* Map U3 config space. We assume all IO-APICs are on the primary bus in mpic_scan_ht_pics()
611 /* Determine if the linux irq is an IPI */
614 return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]); in mpic_is_ipi()
620 return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]); in mpic_is_tm()
635 /* Get the mpic structure from the IPI number */
671 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src); in mpic_unmask_irq()
678 if (!loops--) { in mpic_unmask_irq()
692 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src); in mpic_mask_irq()
700 if (!loops--) { in mpic_mask_irq()
713 DBG("%s: end_irq: %d\n", mpic->name, d->irq); in mpic_end_irq()
762 DBG("%s: end_irq: %d\n", mpic->name, d->irq); in mpic_end_ht_irq()
780 unsigned int src = virq_to_hw(d->irq) - mpic->ipi_vecs[0]; in mpic_unmask_ipi()
782 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src); in mpic_unmask_ipi()
788 /* NEVER disable an IPI... that's just plain wrong! */ in mpic_mask_ipi()
798 * applying to them. We EOI them late to avoid re-entering. in mpic_end_ipi()
808 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0]; in mpic_unmask_tm()
810 DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, d->irq, src); in mpic_unmask_tm()
818 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0]; in mpic_mask_tm()
830 if (mpic->flags & MPIC_SINGLE_DEST_CPU) { in mpic_set_affinity()
874 mpic, d->irq, src, flow_type); in mpic_set_irq_type()
876 if (src >= mpic->num_sources) in mpic_set_irq_type()
877 return -EINVAL; in mpic_set_irq_type()
936 if (src >= mpic->num_sources) in mpic_set_vector()
953 if (src >= mpic->num_sources) in mpic_set_destination()
1003 struct mpic *mpic = h->host_data; in mpic_host_map()
1008 if (hw == mpic->spurious_vec) in mpic_host_map()
1009 return -EINVAL; in mpic_host_map()
1010 if (mpic->protected && test_bit(hw, mpic->protected)) { in mpic_host_map()
1013 return -EPERM; in mpic_host_map()
1017 else if (hw >= mpic->ipi_vecs[0]) { in mpic_host_map()
1018 WARN_ON(mpic->flags & MPIC_SECONDARY); in mpic_host_map()
1020 DBG("mpic: mapping as IPI\n"); in mpic_host_map()
1022 irq_set_chip_and_handler(virq, &mpic->hc_ipi, in mpic_host_map()
1028 if (hw >= mpic->timer_vecs[0] && hw <= mpic->timer_vecs[7]) { in mpic_host_map()
1029 WARN_ON(mpic->flags & MPIC_SECONDARY); in mpic_host_map()
1033 irq_set_chip_and_handler(virq, &mpic->hc_tm, in mpic_host_map()
1041 if (hw >= mpic->num_sources) { in mpic_host_map()
1044 return -EINVAL; in mpic_host_map()
1050 chip = &mpic->hc_irq; in mpic_host_map()
1055 chip = &mpic->hc_ht_irq; in mpic_host_map()
1066 /* If the MPIC was reset, then all vectors have already been in mpic_host_map()
1070 if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) { in mpic_host_map()
1090 struct mpic *mpic = h->host_data; in mpic_host_xlate()
1099 if (intsize >= 4 && (mpic->flags & MPIC_FSL)) { in mpic_host_xlate()
1103 * an "interrupt type". Fourth is type-specific data. in mpic_host_xlate()
1111 if (!(mpic->flags & MPIC_FSL_HAS_EIMR)) in mpic_host_xlate()
1114 if (intspec[3] >= ARRAY_SIZE(mpic->err_int_vecs)) in mpic_host_xlate()
1115 return -EINVAL; in mpic_host_xlate()
1117 *out_hwirq = mpic->err_int_vecs[intspec[3]]; in mpic_host_xlate()
1121 if (intspec[0] >= ARRAY_SIZE(mpic->ipi_vecs)) in mpic_host_xlate()
1122 return -EINVAL; in mpic_host_xlate()
1124 *out_hwirq = mpic->ipi_vecs[intspec[0]]; in mpic_host_xlate()
1127 if (intspec[0] >= ARRAY_SIZE(mpic->timer_vecs)) in mpic_host_xlate()
1128 return -EINVAL; in mpic_host_xlate()
1130 *out_hwirq = mpic->timer_vecs[intspec[0]]; in mpic_host_xlate()
1135 return -EINVAL; in mpic_host_xlate()
1171 BUG_ON(!(mpic->flags & MPIC_SECONDARY)); in mpic_cascade()
1177 chip->irq_eoi(&desc->irq_data); in mpic_cascade()
1190 if (!(mpic->flags & MPIC_FSL)) in fsl_mpic_get_version()
1193 brr1 = _mpic_read(mpic->reg_type, &mpic->thiscpuregs, in fsl_mpic_get_version()
1230 { .type = "open-pic", }, in mpic_alloc()
1231 { .compatible = "open-pic", }, in mpic_alloc()
1236 * If we were not passed a device-tree node, then perform the default in mpic_alloc()
1249 /* Check if it is DCR-based */ in mpic_alloc()
1250 if (of_property_read_bool(node, "dcr-reg")) { in mpic_alloc()
1260 /* Read extra device-tree properties into the flags variable */ in mpic_alloc()
1261 if (of_get_property(node, "big-endian", NULL)) in mpic_alloc()
1263 if (of_get_property(node, "pic-no-reset", NULL)) in mpic_alloc()
1265 if (of_get_property(node, "single-cpu-affinity", NULL)) in mpic_alloc()
1277 mpic->name = name; in mpic_alloc()
1278 mpic->node = node; in mpic_alloc()
1279 mpic->paddr = phys_addr; in mpic_alloc()
1280 mpic->flags = flags; in mpic_alloc()
1282 mpic->hc_irq = mpic_irq_chip; in mpic_alloc()
1283 mpic->hc_irq.name = name; in mpic_alloc()
1284 if (!(mpic->flags & MPIC_SECONDARY)) in mpic_alloc()
1285 mpic->hc_irq.irq_set_affinity = mpic_set_affinity; in mpic_alloc()
1287 mpic->hc_ht_irq = mpic_irq_ht_chip; in mpic_alloc()
1288 mpic->hc_ht_irq.name = name; in mpic_alloc()
1289 if (!(mpic->flags & MPIC_SECONDARY)) in mpic_alloc()
1290 mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity; in mpic_alloc()
1294 mpic->hc_ipi = mpic_ipi_chip; in mpic_alloc()
1295 mpic->hc_ipi.name = name; in mpic_alloc()
1298 mpic->hc_tm = mpic_tm_chip; in mpic_alloc()
1299 mpic->hc_tm.name = name; in mpic_alloc()
1301 mpic->num_sources = 0; /* so far */ in mpic_alloc()
1303 if (mpic->flags & MPIC_LARGE_VECTORS) in mpic_alloc()
1308 mpic->timer_vecs[0] = intvec_top - 12; in mpic_alloc()
1309 mpic->timer_vecs[1] = intvec_top - 11; in mpic_alloc()
1310 mpic->timer_vecs[2] = intvec_top - 10; in mpic_alloc()
1311 mpic->timer_vecs[3] = intvec_top - 9; in mpic_alloc()
1312 mpic->timer_vecs[4] = intvec_top - 8; in mpic_alloc()
1313 mpic->timer_vecs[5] = intvec_top - 7; in mpic_alloc()
1314 mpic->timer_vecs[6] = intvec_top - 6; in mpic_alloc()
1315 mpic->timer_vecs[7] = intvec_top - 5; in mpic_alloc()
1316 mpic->ipi_vecs[0] = intvec_top - 4; in mpic_alloc()
1317 mpic->ipi_vecs[1] = intvec_top - 3; in mpic_alloc()
1318 mpic->ipi_vecs[2] = intvec_top - 2; in mpic_alloc()
1319 mpic->ipi_vecs[3] = intvec_top - 1; in mpic_alloc()
1320 mpic->spurious_vec = intvec_top; in mpic_alloc()
1323 psrc = of_get_property(mpic->node, "protected-sources", &psize); in mpic_alloc()
1327 mpic->protected = kcalloc(mapsize, sizeof(long), GFP_KERNEL); in mpic_alloc()
1328 BUG_ON(mpic->protected == NULL); in mpic_alloc()
1332 __set_bit(psrc[i], mpic->protected); in mpic_alloc()
1337 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(mpic->flags)]; in mpic_alloc()
1341 if (mpic->flags & MPIC_BIG_ENDIAN) in mpic_alloc()
1342 mpic->reg_type = mpic_access_mmio_be; in mpic_alloc()
1344 mpic->reg_type = mpic_access_mmio_le; in mpic_alloc()
1347 * An MPIC with a "dcr-reg" property must be accessed that way, but in mpic_alloc()
1351 if (mpic->flags & MPIC_USES_DCR) in mpic_alloc()
1352 mpic->reg_type = mpic_access_dcr; in mpic_alloc()
1354 BUG_ON(mpic->flags & MPIC_USES_DCR); in mpic_alloc()
1358 mpic_map(mpic, mpic->paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000); in mpic_alloc()
1359 mpic_map(mpic, mpic->paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000); in mpic_alloc()
1361 if (mpic->flags & MPIC_FSL) { in mpic_alloc()
1366 * magic per-cpu area -- and they don't even show up in the in mpic_alloc()
1367 * non-magic per-cpu copies that this driver normally uses. in mpic_alloc()
1369 mpic_map(mpic, mpic->paddr, &mpic->thiscpuregs, in mpic_alloc()
1379 * interrupt vectors. This space is stolen from the in mpic_alloc()
1383 * Available vector space = intvec_top - 13, where 13 in mpic_alloc()
1384 * is the number of vectors which have been consumed by in mpic_alloc()
1388 ret = mpic_setup_error_int(mpic, intvec_top - 13); in mpic_alloc()
1397 * platforms that don't know the MPIC version at compile-time, in mpic_alloc()
1398 * such as qemu-e500, turn off coreint if this MPIC doesn't in mpic_alloc()
1415 /* When using a device-node, reset requests are only honored if the MPIC in mpic_alloc()
1418 if (!(mpic->flags & MPIC_NO_RESET)) { in mpic_alloc()
1420 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), in mpic_alloc()
1421 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) in mpic_alloc()
1423 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) in mpic_alloc()
1429 if (mpic->flags & MPIC_ENABLE_COREINT) in mpic_alloc()
1430 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), in mpic_alloc()
1431 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) in mpic_alloc()
1434 if (mpic->flags & MPIC_ENABLE_MCK) in mpic_alloc()
1435 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), in mpic_alloc()
1436 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) in mpic_alloc()
1445 /* Map the per-CPU registers */ in mpic_alloc()
1449 mpic_map(mpic, mpic->paddr, &mpic->cpuregs[cpu], in mpic_alloc()
1455 * Read feature register. For non-ISU MPICs, num sources as well. On in mpic_alloc()
1458 greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0)); in mpic_alloc()
1462 * device-tree and board support code can override it on buggy hw. in mpic_alloc()
1463 * If we get passed an isu_size (multi-isu MPIC) then we use that in mpic_alloc()
1469 last_irq = isu_size * MPIC_MAX_ISU - 1; in mpic_alloc()
1470 of_property_read_u32(mpic->node, "last-interrupt-source", &last_irq); in mpic_alloc()
1472 last_irq = irq_count - 1; in mpic_alloc()
1477 mpic->num_sources = isu_size; in mpic_alloc()
1478 mpic_map(mpic, mpic->paddr, &mpic->isus[0], in mpic_alloc()
1483 mpic->isu_size = isu_size; in mpic_alloc()
1484 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1); in mpic_alloc()
1485 mpic->isu_mask = (1 << mpic->isu_shift) - 1; in mpic_alloc()
1487 mpic->irqhost = irq_domain_add_linear(mpic->node, in mpic_alloc()
1495 if (mpic->irqhost == NULL) in mpic_alloc()
1515 name, vers, (unsigned long long)mpic->paddr, num_possible_cpus()); in mpic_alloc()
1517 mpic->isu_size, mpic->isu_shift, mpic->isu_mask); in mpic_alloc()
1519 mpic->next = mpics; in mpic_alloc()
1522 if (!(mpic->flags & MPIC_SECONDARY)) { in mpic_alloc()
1524 irq_set_default_host(mpic->irqhost); in mpic_alloc()
1537 unsigned int isu_first = isu_num * mpic->isu_size; in mpic_assign_isu()
1542 paddr, &mpic->isus[isu_num], 0, in mpic_assign_isu()
1543 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); in mpic_assign_isu()
1545 if ((isu_first + mpic->isu_size) > mpic->num_sources) in mpic_assign_isu()
1546 mpic->num_sources = isu_first + mpic->isu_size; in mpic_assign_isu()
1554 BUG_ON(mpic->num_sources == 0); in mpic_init()
1556 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources); in mpic_init()
1561 if (mpic->flags & MPIC_FSL) { in mpic_init()
1574 /* Initialize timers to our reserved vectors and mask them for now */ in mpic_init()
1578 mpic_write(mpic->tmregs, in mpic_init()
1581 mpic_write(mpic->tmregs, in mpic_init()
1585 (mpic->timer_vecs[0] + i)); in mpic_init()
1588 /* Initialize IPIs to our reserved vectors and mark them disabled for now */ in mpic_init()
1594 (mpic->ipi_vecs[0] + i)); in mpic_init()
1598 DBG("MPIC flags: %x\n", mpic->flags); in mpic_init()
1599 if ((mpic->flags & MPIC_U3_HT_IRQS) && !(mpic->flags & MPIC_SECONDARY)) { in mpic_init()
1608 if (!(mpic->flags & MPIC_NO_RESET)) { in mpic_init()
1609 for (i = 0; i < mpic->num_sources; i++) { in mpic_init()
1615 if (mpic->protected && test_bit(i, mpic->protected)) in mpic_init()
1624 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec); in mpic_init()
1627 if (!(mpic->flags & MPIC_NO_PTHROU_DIS)) in mpic_init()
1628 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), in mpic_init()
1629 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) in mpic_init()
1632 if (mpic->flags & MPIC_NO_BIAS) in mpic_init()
1633 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), in mpic_init()
1634 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) in mpic_init()
1642 mpic->save_data = kmalloc_array(mpic->num_sources, in mpic_init()
1643 sizeof(*mpic->save_data), in mpic_init()
1645 BUG_ON(mpic->save_data == NULL); in mpic_init()
1649 if (mpic->flags & MPIC_SECONDARY) { in mpic_init()
1650 int virq = irq_of_parse_and_map(mpic->node, 0); in mpic_init()
1653 mpic->node, virq); in mpic_init()
1660 if (mpic->flags & MPIC_FSL_HAS_EIMR) in mpic_init()
1676 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) & in mpic_irq_set_priority()
1678 mpic_ipi_write(src - mpic->ipi_vecs[0], in mpic_irq_set_priority()
1681 reg = mpic_tm_read(src - mpic->timer_vecs[0]) & in mpic_irq_set_priority()
1683 mpic_tm_write(src - mpic->timer_vecs[0], in mpic_irq_set_priority()
1704 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); in mpic_setup_this_cpu()
1713 if (distribute_irqs && !(mpic->flags & MPIC_SINGLE_DEST_CPU)) { in mpic_setup_this_cpu()
1714 for (i = 0; i < mpic->num_sources ; i++) in mpic_setup_this_cpu()
1750 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); in mpic_teardown_this_cpu()
1754 for (i = 0; i < mpic->num_sources ; i++) in mpic_teardown_this_cpu()
1760 /* We need to EOI the IPI since not all platforms reset the MPIC in mpic_teardown_this_cpu()
1775 DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src); in _mpic_get_one_irq()
1777 if (unlikely(src == mpic->spurious_vec)) { in _mpic_get_one_irq()
1778 if (mpic->flags & MPIC_SPV_EOI) in _mpic_get_one_irq()
1782 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) { in _mpic_get_one_irq()
1784 mpic->name, (int)src); in _mpic_get_one_irq()
1789 return irq_linear_revmap(mpic->irqhost, src); in _mpic_get_one_irq()
1816 if (unlikely(src == mpic->spurious_vec)) { in mpic_get_coreint_irq()
1817 if (mpic->flags & MPIC_SPV_EOI) in mpic_get_coreint_irq()
1821 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) { in mpic_get_coreint_irq()
1823 mpic->name, (int)src); in mpic_get_coreint_irq()
1827 return irq_linear_revmap(mpic->irqhost, src); in mpic_get_coreint_irq()
1852 unsigned int vipi = irq_create_mapping(mpic->irqhost, in mpic_request_ipis()
1853 mpic->ipi_vecs[0] + i); in mpic_request_ipis()
1869 /* make sure we're sending something that translates to an IPI */ in smp_mpic_message_pass()
1877 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, msg); in smp_mpic_message_pass()
1913 pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); in mpic_reset_core()
1915 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir); in mpic_reset_core()
1916 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); in mpic_reset_core()
1920 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir); in mpic_reset_core()
1921 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); in mpic_reset_core()
1925 if (mpic->flags & MPIC_FSL) { in mpic_reset_core()
1927 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpuid], in mpic_reset_core()
1939 for (i = 0; i < mpic->num_sources; i++) { in mpic_suspend_one()
1940 mpic->save_data[i].vecprio = in mpic_suspend_one()
1942 mpic->save_data[i].dest = in mpic_suspend_one()
1953 mpic = mpic->next; in mpic_suspend()
1963 for (i = 0; i < mpic->num_sources; i++) { in mpic_resume_one()
1965 mpic->save_data[i].vecprio); in mpic_resume_one()
1967 mpic->save_data[i].dest); in mpic_resume_one()
1970 if (mpic->fixups) { in mpic_resume_one()
1971 struct mpic_irq_fixup *fixup = &mpic->fixups[i]; in mpic_resume_one()
1973 if (fixup->base) { in mpic_resume_one()
1975 if ((mpic->save_data[i].fixup_data & 1) == 0) in mpic_resume_one()
1979 writeb(0x10 + 2 * fixup->index, fixup->base + 2); in mpic_resume_one()
1981 writel(mpic->save_data[i].fixup_data & ~1, in mpic_resume_one()
1982 fixup->base + 4); in mpic_resume_one()
1995 mpic = mpic->next; in mpic_resume()