17  * the need to put the MMIO space for each VF into a separate PE. Internally
18  * the PHB maps MMIO addresses to a specific PE using the "Memory BAR Table".
42  *    segments. The n'th segment is mapped to the n'th PE.
43  * b) An un-segmented BAR that maps the whole address range to a specific PE.
84  *    This is where we actually allocate PE numbers for each VF and setup the
88  *    ability because the PE space is shared by all devices on the same PHB.
89  *    When using mode a) described above segment 0 in maps to PE#0 which might
92  *    As a result we need allocate a contigious range of PE numbers, then shift
95  *    PE number. This is handled in pnv_pci_vf_resource_shift().
100  *    PE that we allocated for it rather than the PE associated with the bus.
107  * That's how mode a) works. In theory mode b) (single PE mapping) is less work
132  *    mapped to any PE. This is matches how the 32bit MMIO window worked on
136  *    but with fewer segments and configurable base PE.
138  *    i.e. The n'th segment maps to the (n + base)'th PE.
140  *    The base PE is also required to be a multiple of the window size.
177 		 * then each VF BAR should be mapped in single-PE mode to reduce  in pnv_pci_ioda_fixup_iov_resources()
192 				pci_err(pdev, "VF BAR%d: %pR can't be mapped in single PE mode\n",  in pnv_pci_ioda_fixup_iov_resources()
209 		pci_info(pdev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",  in pnv_pci_ioda_fixup_iov_resources()
235 		struct pnv_ioda_pe *pe = pnv_ioda_get_pe(pdev);  in pnv_pci_ioda_fixup_iov()  local
239 		 * be set. The pdev doesn't exist when the PE is allocated (in  in pnv_pci_ioda_fixup_iov()
242 		pe->pdev = pdev;  in pnv_pci_ioda_fixup_iov()
243 		WARN_ON(!(pe->flags & PNV_IODA_PE_VF));  in pnv_pci_ioda_fixup_iov()
264 	 * BARs would not be placed in the correct PE.  in pnv_pci_iov_resource_alignment()
271 	 * alignment. We validated that it's possible to use a single PE  in pnv_pci_iov_resource_alignment()
283 	 * Shared PE mode or just VF BAR size if not.  in pnv_pci_iov_resource_alignment()
284 	 * If the M64 BAR is in Single PE mode, return the VF BAR size or  in pnv_pci_iov_resource_alignment()
356 	 * assigned to a PE.  in pnv_ioda_map_m64_single()
361 	 * single PE windows added in PHB3 don't map cleanly to this API.  in pnv_ioda_map_m64_single()
365 	 * PE mode, and set the PE for the window before setting the address  in pnv_ioda_map_m64_single()
366 	 * bounds. We need to do it this way because the single PE windows  in pnv_ioda_map_m64_single()
378 	 * NB: In single PE mode the window needs to be aligned to 32MB  in pnv_ioda_map_m64_single()
391 	 * mode so FW will validate that the BAR is in single PE mode.  in pnv_ioda_map_m64_single()
399 		pr_err("Error mapping single PE BAR\n");  in pnv_ioda_map_m64_single()
456 		/* otherwise map each VF with single PE BARs */  in pnv_pci_vf_assign_m64()
484 	struct pnv_ioda_pe    *pe, *pe_n;  in pnv_ioda_release_vf_PE()  local
492 	list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {  in pnv_ioda_release_vf_PE()
493 		if (pe->parent_dev != pdev)  in pnv_ioda_release_vf_PE()
496 		pnv_pci_ioda2_release_pe_dma(pe);  in pnv_ioda_release_vf_PE()
500 		list_del(&pe->list);  in pnv_ioda_release_vf_PE()
503 		pnv_ioda_deconfigure_pe(phb, pe);  in pnv_ioda_release_vf_PE()
505 		pnv_ioda_free_pe(pe);  in pnv_ioda_release_vf_PE()
524 	 * Each segment is in a separate PE, and the high order bits of the  in pnv_pci_vf_resource_shift()
525 	 * address are the PE number.  Therefore, each VF's BAR is in a  in pnv_pci_vf_resource_shift()
526 	 * separate PE, and changing the IOV BAR start address changes the  in pnv_pci_vf_resource_shift()
558 	 * the segment which belongs to the PE number assigned to the first VF.  in pnv_pci_vf_resource_shift()
623 	struct pnv_ioda_pe    *pe;  in pnv_ioda_setup_vf_PE()  local
636 	/* Reserve PE for each VF */  in pnv_ioda_setup_vf_PE()
642 		pe = &iov->vf_pe_arr[vf_index];  in pnv_ioda_setup_vf_PE()
643 		pe->phb = phb;  in pnv_ioda_setup_vf_PE()
644 		pe->flags = PNV_IODA_PE_VF;  in pnv_ioda_setup_vf_PE()
645 		pe->pbus = NULL;  in pnv_ioda_setup_vf_PE()
646 		pe->parent_dev = pdev;  in pnv_ioda_setup_vf_PE()
647 		pe->mve_number = -1;  in pnv_ioda_setup_vf_PE()
648 		pe->rid = (vf_bus << 8) | vf_devfn;  in pnv_ioda_setup_vf_PE()
650 		pe_num = pe->pe_number;  in pnv_ioda_setup_vf_PE()
651 		pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n",  in pnv_ioda_setup_vf_PE()
655 		if (pnv_ioda_configure_pe(phb, pe)) {  in pnv_ioda_setup_vf_PE()
657 			pnv_ioda_free_pe(pe);  in pnv_ioda_setup_vf_PE()
658 			pe->pdev = NULL;  in pnv_ioda_setup_vf_PE()
662 		/* Put PE to the list */  in pnv_ioda_setup_vf_PE()
664 		list_add_tail(&pe->list, &phb->ioda.pe_list);  in pnv_ioda_setup_vf_PE()
667 		/* associate this pe to it's pdn */  in pnv_ioda_setup_vf_PE()
676 		pnv_pci_ioda2_setup_dma_pe(phb, pe);  in pnv_ioda_setup_vf_PE()
692 	 * There's a calls to IODA2 PE setup code littered throughout. We could  in pnv_pci_sriov_enable()
727 	 * the IOV BAR according to the PE# allocated to the VFs.  in pnv_pci_sriov_enable()
728 	 * Otherwise, the PE# for the VF will conflict with others.  in pnv_pci_sriov_enable()