18  * the PHB maps MMIO addresses to a specific PE using the "Memory BAR Table".
27  * For a SR-IOV BAR things are a little more awkward since size and alignment
28  * are not coupled. The alignment is set based on the the per-VF BAR size, but
29  * the total BAR area is: number-of-vfs * per-vf-size. The number of VFs
31  * we need to finesse (read: hack) the Linux BAR allocator so that it will
36  * so as a baseline we can assume that we have the following BAR modes
41  * a) A segmented BAR that splits the mapped range into $PE_COUNT equally sized
43  * b) An un-segmented BAR that maps the whole address range to a specific PE.
46  * We prefer to use mode a) since it only requires one MBT entry per SR-IOV BAR
47  * For comparison b) requires one entry per-VF per-BAR, or:
49  * to equal the size of the per-VF BAR area. So:
53  * The alignment for the SR-IOV BAR also needs to be changed from per-vf-size
85  *    MBT mapping for each SR-IOV BAR. In steps 1) and 2) we setup an "arena"
86  *    where each MBT segment is equal in size to the VF BAR so we can shift
87  *    around the actual SR-IOV BAR location within this arena. We need this
93  *    the address programmed into the SR-IOV BAR of the PF so that the address
108  * since we can map each individual VF with a separate BAR. However, there's a
127  * the Linux BAR allocation will place any BAR marked as non-prefetchable into
131  * c) A segmented BAR similar to a), but each segment can be individually
135  * d) A segmented BAR with 8, 64, or 128 segments. This works similarly to a),
166 			dev_warn(&pdev->dev, "Don't support SR-IOV with non M64 VF BAR%d: %pR. \n",  in pnv_pci_ioda_fixup_iov_resources()
174 		 * Generally, one segmented M64 BAR maps one IOV BAR. However,  in pnv_pci_ioda_fixup_iov_resources()
175 		 * if a VF BAR is too large we end up wasting a lot of space.  in pnv_pci_ioda_fixup_iov_resources()
177 		 * then each VF BAR should be mapped in single-PE mode to reduce  in pnv_pci_ioda_fixup_iov_resources()
185 			 * On PHB3, the minimum size alignment of M64 BAR in  in pnv_pci_ioda_fixup_iov_resources()
186 			 * single mode is 32MB. If this VF BAR is smaller than  in pnv_pci_ioda_fixup_iov_resources()
192 				pci_err(pdev, "VF BAR%d: %pR can't be mapped in single PE mode\n",  in pnv_pci_ioda_fixup_iov_resources()
202 		 * This BAR can be mapped with one segmented window, so adjust  in pnv_pci_ioda_fixup_iov_resources()
205 		pci_dbg(pdev, " Fixing VF BAR%d: %pR to\n", i, res);  in pnv_pci_ioda_fixup_iov_resources()
209 		pci_info(pdev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",  in pnv_pci_ioda_fixup_iov_resources()
247 		 * the PHB can support using it's M64 BAR table.  in pnv_pci_ioda_fixup_iov()
261 	 * iov can be null if we have an SR-IOV device with IOV BAR that can't  in pnv_pci_iov_resource_alignment()
262 	 * be placed in the m64 space (i.e. The BAR is 32bit or non-prefetch).  in pnv_pci_iov_resource_alignment()
270 	 * If we're using single mode then we can just use the native VF BAR  in pnv_pci_iov_resource_alignment()
278 	 * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the  in pnv_pci_iov_resource_alignment()
280 	 * BAR should be size aligned.  in pnv_pci_iov_resource_alignment()
282 	 * This function returns the total IOV BAR size if M64 BAR is in  in pnv_pci_iov_resource_alignment()
283 	 * Shared PE mode or just VF BAR size if not.  in pnv_pci_iov_resource_alignment()
284 	 * If the M64 BAR is in Single PE mode, return the VF BAR size or  in pnv_pci_iov_resource_alignment()
285 	 * M64 segment size if IOV BAR size is less.  in pnv_pci_iov_resource_alignment()
354 	 * with P7-IOC in mind. For that chip each M64 BAR (window) had a fixed  in pnv_ioda_map_m64_single()
359 	 * communicate the number of segments we want on a BAR. This wasn't  in pnv_ioda_map_m64_single()
390 	 * Now actually enable it. We specified the BAR should be in "non-split"  in pnv_ioda_map_m64_single()
391 	 * mode so FW will validate that the BAR is in single PE mode.  in pnv_ioda_map_m64_single()
399 		pr_err("Error mapping single PE BAR\n");  in pnv_ioda_map_m64_single()
523 	 * are segmented, each segment is the same size as the IOV BAR.  in pnv_pci_vf_resource_shift()
525 	 * address are the PE number.  Therefore, each VF's BAR is in a  in pnv_pci_vf_resource_shift()
526 	 * separate PE, and changing the IOV BAR start address changes the  in pnv_pci_vf_resource_shift()
538 		 * The actual IOV BAR range is determined by the start address  in pnv_pci_vf_resource_shift()
539 		 * and the actual size for num_vfs VFs BAR.  This check is to  in pnv_pci_vf_resource_shift()
549 …dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",  in pnv_pci_vf_resource_shift()
556 	 * Since M64 BAR shares segments among all possible 256 PEs,  in pnv_pci_vf_resource_shift()
557 	 * we have to shift the beginning of PF IOV BAR to make it start from  in pnv_pci_vf_resource_shift()
574 		dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n",  in pnv_pci_vf_resource_shift()
704 		dev_info(&pdev->dev, "don't support this SRIOV device with non 64bit-prefetchable IOV BAR\n");  in pnv_pci_sriov_enable()
726 	 * When using one M64 BAR to map one IOV BAR, we need to shift  in pnv_pci_sriov_enable()
727 	 * the IOV BAR according to the PE# allocated to the VFs.  in pnv_pci_sriov_enable()