Lines Matching full:pe
53 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
56 void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, in pe_level_printk() argument
68 if (pe->flags & PNV_IODA_PE_DEV) in pe_level_printk()
69 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); in pe_level_printk()
70 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) in pe_level_printk()
72 pci_domain_nr(pe->pbus), pe->pbus->number); in pe_level_printk()
74 else if (pe->flags & PNV_IODA_PE_VF) in pe_level_printk()
76 pci_domain_nr(pe->parent_dev->bus), in pe_level_printk()
77 (pe->rid & 0xff00) >> 8, in pe_level_printk()
78 PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); in pe_level_printk()
81 printk("%spci %s: [PE# %.2x] %pV", in pe_level_printk()
82 level, pfix, pe->pe_number, &vaf); in pe_level_printk()
127 * Clear the PE frozen state as it might be put into frozen state in pnv_ioda_init_pe()
129 * PE is already in unfrozen state. in pnv_ioda_init_pe()
134 pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n", in pnv_ioda_init_pe()
143 pr_warn("%s: Invalid PE %x on PHB#%x\n", in pnv_ioda_reserve_pe()
150 pr_debug("%s: PE %x was reserved on PHB#%x\n", in pnv_ioda_reserve_pe()
160 int run = 0, pe, i; in pnv_ioda_alloc_pe() local
165 for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) { in pnv_ioda_alloc_pe()
166 if (test_bit(pe, phb->ioda.pe_alloc)) { in pnv_ioda_alloc_pe()
178 for (i = pe; i < pe + count; i++) { in pnv_ioda_alloc_pe()
182 ret = &phb->ioda.pe_array[pe]; in pnv_ioda_alloc_pe()
189 void pnv_ioda_free_pe(struct pnv_ioda_pe *pe) in pnv_ioda_free_pe() argument
191 struct pnv_phb *phb = pe->phb; in pnv_ioda_free_pe()
192 unsigned int pe_num = pe->pe_number; in pnv_ioda_free_pe()
194 WARN_ON(pe->pdev); in pnv_ioda_free_pe()
195 WARN_ON(pe->npucomp); /* NPUs for nvlink are not supposed to be freed */ in pnv_ioda_free_pe()
196 kfree(pe->npucomp); in pnv_ioda_free_pe()
197 memset(pe, 0, sizeof(struct pnv_ioda_pe)); in pnv_ioda_free_pe()
234 * Exclude the segments for reserved and root bus PE, which in pnv_ioda2_init_m64()
243 pr_warn(" Cannot strip M64 segment for reserved PE#%x\n", in pnv_ioda2_init_m64()
324 * to one particular PE#. However, PHB3 has fixed mapping in pnv_ioda1_init_m64()
325 * between M64 segment and PE#. In order to have same logic in pnv_ioda1_init_m64()
327 * segment and PE# on P7IOC. in pnv_ioda1_init_m64()
334 pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n", in pnv_ioda1_init_m64()
342 * Exclude the segments for reserved and root bus PE, which in pnv_ioda1_init_m64()
351 WARN(1, "Wrong reserved PE#%x on PHB#%x\n", in pnv_ioda1_init_m64()
382 struct pnv_ioda_pe *master_pe, *pe; in pnv_ioda_pick_m64_pe() local
399 /* Figure out reserved PE numbers by the PE */ in pnv_ioda_pick_m64_pe()
405 * pick M64 dependent PE#. in pnv_ioda_pick_m64_pe()
413 * Figure out the master PE and put all slave PEs to master in pnv_ioda_pick_m64_pe()
414 * PE's list to form compound PE. in pnv_ioda_pick_m64_pe()
420 pe = &phb->ioda.pe_array[i]; in pnv_ioda_pick_m64_pe()
422 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; in pnv_ioda_pick_m64_pe()
424 pe->flags |= PNV_IODA_PE_MASTER; in pnv_ioda_pick_m64_pe()
425 INIT_LIST_HEAD(&pe->slaves); in pnv_ioda_pick_m64_pe()
426 master_pe = pe; in pnv_ioda_pick_m64_pe()
428 pe->flags |= PNV_IODA_PE_SLAVE; in pnv_ioda_pick_m64_pe()
429 pe->master = master_pe; in pnv_ioda_pick_m64_pe()
430 list_add_tail(&pe->list, &master_pe->slaves); in pnv_ioda_pick_m64_pe()
530 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; in pnv_ioda_freeze_pe() local
534 /* Fetch master PE */ in pnv_ioda_freeze_pe()
535 if (pe->flags & PNV_IODA_PE_SLAVE) { in pnv_ioda_freeze_pe()
536 pe = pe->master; in pnv_ioda_freeze_pe()
537 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) in pnv_ioda_freeze_pe()
540 pe_no = pe->pe_number; in pnv_ioda_freeze_pe()
543 /* Freeze master PE */ in pnv_ioda_freeze_pe()
548 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", in pnv_ioda_freeze_pe()
554 if (!(pe->flags & PNV_IODA_PE_MASTER)) in pnv_ioda_freeze_pe()
557 list_for_each_entry(slave, &pe->slaves, list) { in pnv_ioda_freeze_pe()
562 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", in pnv_ioda_freeze_pe()
570 struct pnv_ioda_pe *pe, *slave; in pnv_ioda_unfreeze_pe() local
573 /* Find master PE */ in pnv_ioda_unfreeze_pe()
574 pe = &phb->ioda.pe_array[pe_no]; in pnv_ioda_unfreeze_pe()
575 if (pe->flags & PNV_IODA_PE_SLAVE) { in pnv_ioda_unfreeze_pe()
576 pe = pe->master; in pnv_ioda_unfreeze_pe()
577 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); in pnv_ioda_unfreeze_pe()
578 pe_no = pe->pe_number; in pnv_ioda_unfreeze_pe()
581 /* Clear frozen state for master PE */ in pnv_ioda_unfreeze_pe()
584 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", in pnv_ioda_unfreeze_pe()
589 if (!(pe->flags & PNV_IODA_PE_MASTER)) in pnv_ioda_unfreeze_pe()
593 list_for_each_entry(slave, &pe->slaves, list) { in pnv_ioda_unfreeze_pe()
598 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", in pnv_ioda_unfreeze_pe()
610 struct pnv_ioda_pe *slave, *pe; in pnv_ioda_get_pe_state() local
615 /* Sanity check on PE number */ in pnv_ioda_get_pe_state()
620 * Fetch the master PE and the PE instance might be in pnv_ioda_get_pe_state()
623 pe = &phb->ioda.pe_array[pe_no]; in pnv_ioda_get_pe_state()
624 if (pe->flags & PNV_IODA_PE_SLAVE) { in pnv_ioda_get_pe_state()
625 pe = pe->master; in pnv_ioda_get_pe_state()
626 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); in pnv_ioda_get_pe_state()
627 pe_no = pe->pe_number; in pnv_ioda_get_pe_state()
630 /* Check the master PE */ in pnv_ioda_get_pe_state()
635 "PHB#%x-PE#%x state\n", in pnv_ioda_get_pe_state()
641 /* Check the slave PE */ in pnv_ioda_get_pe_state()
642 if (!(pe->flags & PNV_IODA_PE_MASTER)) in pnv_ioda_get_pe_state()
645 list_for_each_entry(slave, &pe->slaves, list) { in pnv_ioda_get_pe_state()
653 "PHB#%x-PE#%x state\n", in pnv_ioda_get_pe_state()
703 /* Parent PE affects child PE */ in pnv_ioda_set_one_peltv()
715 /* Compound case: parent PE affects slave PEs */ in pnv_ioda_set_one_peltv()
730 struct pnv_ioda_pe *pe, in pnv_ioda_set_peltv() argument
738 * Clear PE frozen state. If it's master PE, we need in pnv_ioda_set_peltv()
739 * clear slave PE frozen state as well. in pnv_ioda_set_peltv()
742 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, in pnv_ioda_set_peltv()
744 if (pe->flags & PNV_IODA_PE_MASTER) { in pnv_ioda_set_peltv()
745 list_for_each_entry(slave, &pe->slaves, list) in pnv_ioda_set_peltv()
753 * Associate PE in PELT. We need add the PE into the in pnv_ioda_set_peltv()
755 * originated from the PE might contribute to other in pnv_ioda_set_peltv()
758 ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); in pnv_ioda_set_peltv()
763 if (pe->flags & PNV_IODA_PE_MASTER) { in pnv_ioda_set_peltv()
764 list_for_each_entry(slave, &pe->slaves, list) { in pnv_ioda_set_peltv()
765 ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); in pnv_ioda_set_peltv()
771 if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) in pnv_ioda_set_peltv()
772 pdev = pe->pbus->self; in pnv_ioda_set_peltv()
773 else if (pe->flags & PNV_IODA_PE_DEV) in pnv_ioda_set_peltv()
774 pdev = pe->pdev->bus->self; in pnv_ioda_set_peltv()
776 else if (pe->flags & PNV_IODA_PE_VF) in pnv_ioda_set_peltv()
777 pdev = pe->parent_dev; in pnv_ioda_set_peltv()
785 ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); in pnv_ioda_set_peltv()
797 struct pnv_ioda_pe *pe, in pnv_ioda_unset_peltv() argument
807 pe->pe_number, in pnv_ioda_unset_peltv()
814 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, in pnv_ioda_unset_peltv()
817 /* Disassociate PE in PELT */ in pnv_ioda_unset_peltv()
818 rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, in pnv_ioda_unset_peltv()
819 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); in pnv_ioda_unset_peltv()
821 pe_warn(pe, "OPAL error %lld remove self from PELTV\n", rc); in pnv_ioda_unset_peltv()
824 int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) in pnv_ioda_deconfigure_pe() argument
831 /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ in pnv_ioda_deconfigure_pe()
832 if (pe->pbus) { in pnv_ioda_deconfigure_pe()
837 parent = pe->pbus->self; in pnv_ioda_deconfigure_pe()
838 if (pe->flags & PNV_IODA_PE_BUS_ALL) in pnv_ioda_deconfigure_pe()
839 count = resource_size(&pe->pbus->busn_res); in pnv_ioda_deconfigure_pe()
851 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", in pnv_ioda_deconfigure_pe()
856 rid_end = pe->rid + (count << 8); in pnv_ioda_deconfigure_pe()
859 if (pe->flags & PNV_IODA_PE_VF) in pnv_ioda_deconfigure_pe()
860 parent = pe->parent_dev; in pnv_ioda_deconfigure_pe()
863 parent = pe->pdev->bus->self; in pnv_ioda_deconfigure_pe()
867 rid_end = pe->rid + 1; in pnv_ioda_deconfigure_pe()
871 for (rid = pe->rid; rid < rid_end; rid++) in pnv_ioda_deconfigure_pe()
879 pnv_ioda_unset_peltv(phb, pe, parent); in pnv_ioda_deconfigure_pe()
881 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, in pnv_ioda_deconfigure_pe()
884 pe_err(pe, "OPAL error %lld trying to setup PELT table\n", rc); in pnv_ioda_deconfigure_pe()
886 pe->pbus = NULL; in pnv_ioda_deconfigure_pe()
887 pe->pdev = NULL; in pnv_ioda_deconfigure_pe()
889 pe->parent_dev = NULL; in pnv_ioda_deconfigure_pe()
895 int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) in pnv_ioda_configure_pe() argument
901 if (pe->pbus) { in pnv_ioda_configure_pe()
906 if (pe->flags & PNV_IODA_PE_BUS_ALL) in pnv_ioda_configure_pe()
907 count = resource_size(&pe->pbus->busn_res); in pnv_ioda_configure_pe()
919 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", in pnv_ioda_configure_pe()
924 rid_end = pe->rid + (count << 8); in pnv_ioda_configure_pe()
929 rid_end = pe->rid + 1; in pnv_ioda_configure_pe()
933 * Associate PE in PELT. We need add the PE into the in pnv_ioda_configure_pe()
935 * originated from the PE might contribute to other in pnv_ioda_configure_pe()
938 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, in pnv_ioda_configure_pe()
941 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); in pnv_ioda_configure_pe()
950 pnv_ioda_set_peltv(phb, pe, true); in pnv_ioda_configure_pe()
953 for (rid = pe->rid; rid < rid_end; rid++) in pnv_ioda_configure_pe()
954 phb->ioda.pe_rmap[rid] = pe->pe_number; in pnv_ioda_configure_pe()
958 pe->mve_number = 0; in pnv_ioda_configure_pe()
962 pe->mve_number = pe->pe_number; in pnv_ioda_configure_pe()
963 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); in pnv_ioda_configure_pe()
965 pe_err(pe, "OPAL error %ld setting up MVE %x\n", in pnv_ioda_configure_pe()
966 rc, pe->mve_number); in pnv_ioda_configure_pe()
967 pe->mve_number = -1; in pnv_ioda_configure_pe()
970 pe->mve_number, OPAL_ENABLE_MVE); in pnv_ioda_configure_pe()
972 pe_err(pe, "OPAL error %ld enabling MVE %x\n", in pnv_ioda_configure_pe()
973 rc, pe->mve_number); in pnv_ioda_configure_pe()
974 pe->mve_number = -1; in pnv_ioda_configure_pe()
986 struct pnv_ioda_pe *pe; in pnv_ioda_setup_dev_PE() local
996 pe = pnv_ioda_alloc_pe(phb, 1); in pnv_ioda_setup_dev_PE()
997 if (!pe) { in pnv_ioda_setup_dev_PE()
998 pr_warn("%s: Not enough PE# available, disabling device\n", in pnv_ioda_setup_dev_PE()
1003 /* NOTE: We don't get a reference for the pointer in the PE in pnv_ioda_setup_dev_PE()
1004 * data structure, both the device and PE structures should be in pnv_ioda_setup_dev_PE()
1010 pdn->pe_number = pe->pe_number; in pnv_ioda_setup_dev_PE()
1011 pe->flags = PNV_IODA_PE_DEV; in pnv_ioda_setup_dev_PE()
1012 pe->pdev = dev; in pnv_ioda_setup_dev_PE()
1013 pe->pbus = NULL; in pnv_ioda_setup_dev_PE()
1014 pe->mve_number = -1; in pnv_ioda_setup_dev_PE()
1015 pe->rid = dev->bus->number << 8 | pdn->devfn; in pnv_ioda_setup_dev_PE()
1016 pe->device_count++; in pnv_ioda_setup_dev_PE()
1018 pe_info(pe, "Associated device to PE\n"); in pnv_ioda_setup_dev_PE()
1020 if (pnv_ioda_configure_pe(phb, pe)) { in pnv_ioda_setup_dev_PE()
1022 pnv_ioda_free_pe(pe); in pnv_ioda_setup_dev_PE()
1024 pe->pdev = NULL; in pnv_ioda_setup_dev_PE()
1028 /* Put PE to the list */ in pnv_ioda_setup_dev_PE()
1030 list_add_tail(&pe->list, &phb->ioda.pe_list); in pnv_ioda_setup_dev_PE()
1032 return pe; in pnv_ioda_setup_dev_PE()
1038 * subordinate PCI devices and buses. The second type of PE is normally
1044 struct pnv_ioda_pe *pe = NULL; in pnv_ioda_setup_bus_PE() local
1048 * In partial hotplug case, the PE instance might be still alive. in pnv_ioda_setup_bus_PE()
1053 pe = &phb->ioda.pe_array[pe_num]; in pnv_ioda_setup_bus_PE()
1057 /* PE number for root bus should have been reserved */ in pnv_ioda_setup_bus_PE()
1059 pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx]; in pnv_ioda_setup_bus_PE()
1061 /* Check if PE is determined by M64 */ in pnv_ioda_setup_bus_PE()
1062 if (!pe) in pnv_ioda_setup_bus_PE()
1063 pe = pnv_ioda_pick_m64_pe(bus, all); in pnv_ioda_setup_bus_PE()
1065 /* The PE number isn't pinned by M64 */ in pnv_ioda_setup_bus_PE()
1066 if (!pe) in pnv_ioda_setup_bus_PE()
1067 pe = pnv_ioda_alloc_pe(phb, 1); in pnv_ioda_setup_bus_PE()
1069 if (!pe) { in pnv_ioda_setup_bus_PE()
1070 pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n", in pnv_ioda_setup_bus_PE()
1075 pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); in pnv_ioda_setup_bus_PE()
1076 pe->pbus = bus; in pnv_ioda_setup_bus_PE()
1077 pe->pdev = NULL; in pnv_ioda_setup_bus_PE()
1078 pe->mve_number = -1; in pnv_ioda_setup_bus_PE()
1079 pe->rid = bus->busn_res.start << 8; in pnv_ioda_setup_bus_PE()
1082 pe_info(pe, "Secondary bus %pad..%pad associated with PE#%x\n", in pnv_ioda_setup_bus_PE()
1084 pe->pe_number); in pnv_ioda_setup_bus_PE()
1086 pe_info(pe, "Secondary bus %pad associated with PE#%x\n", in pnv_ioda_setup_bus_PE()
1087 &bus->busn_res.start, pe->pe_number); in pnv_ioda_setup_bus_PE()
1089 if (pnv_ioda_configure_pe(phb, pe)) { in pnv_ioda_setup_bus_PE()
1091 pnv_ioda_free_pe(pe); in pnv_ioda_setup_bus_PE()
1092 pe->pbus = NULL; in pnv_ioda_setup_bus_PE()
1096 /* Put PE to the list */ in pnv_ioda_setup_bus_PE()
1097 list_add_tail(&pe->list, &phb->ioda.pe_list); in pnv_ioda_setup_bus_PE()
1099 return pe; in pnv_ioda_setup_bus_PE()
1106 struct pnv_ioda_pe *pe; in pnv_ioda_setup_npu_PE() local
1120 * Due to a hardware errata PE#0 on the NPU is reserved for in pnv_ioda_setup_npu_PE()
1126 * same GPU get assigned the same PE. in pnv_ioda_setup_npu_PE()
1130 pe = &phb->ioda.pe_array[pe_num]; in pnv_ioda_setup_npu_PE()
1131 if (!pe->pdev) in pnv_ioda_setup_npu_PE()
1134 if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) { in pnv_ioda_setup_npu_PE()
1137 * be assigned the same PE as the existing in pnv_ioda_setup_npu_PE()
1141 "Associating to existing PE %x\n", pe_num); in pnv_ioda_setup_npu_PE()
1145 phb->ioda.pe_rmap[rid] = pe->pe_number; in pnv_ioda_setup_npu_PE()
1146 pe->device_count++; in pnv_ioda_setup_npu_PE()
1148 /* Map the PE to this link */ in pnv_ioda_setup_npu_PE()
1162 * Could not find an existing PE so allocate a new in pnv_ioda_setup_npu_PE()
1167 return pe; in pnv_ioda_setup_npu_PE()
1182 struct pnv_ioda_pe *pe; in pnv_pci_ioda_setup_nvlink() local
1187 /* PE#0 is needed for error reporting */ in pnv_pci_ioda_setup_nvlink()
1199 list_for_each_entry(pe, &phb->ioda.pe_list, list) in pnv_pci_ioda_setup_nvlink()
1200 pnv_npu2_map_lpar(pe, MSR_DR | MSR_PR | MSR_HV); in pnv_pci_ioda_setup_nvlink()
1210 struct pnv_ioda_pe *pe);
1216 struct pnv_ioda_pe *pe; in pnv_pci_ioda_dma_dev_setup() local
1218 /* Check if the BDFN for this device is associated with a PE yet */ in pnv_pci_ioda_dma_dev_setup()
1219 pe = pnv_pci_bdfn_to_pe(phb, pdev->devfn | (pdev->bus->number << 8)); in pnv_pci_ioda_dma_dev_setup()
1220 if (!pe) { in pnv_pci_ioda_dma_dev_setup()
1226 pe = pnv_pci_bdfn_to_pe(phb, pdev->devfn | (pdev->bus->number << 8)); in pnv_pci_ioda_dma_dev_setup()
1227 pci_info(pdev, "Configured PE#%x\n", pe ? pe->pe_number : 0xfffff); in pnv_pci_ioda_dma_dev_setup()
1231 * If we can't setup the IODA PE something has gone horribly in pnv_pci_ioda_dma_dev_setup()
1234 if (WARN_ON(!pe)) in pnv_pci_ioda_dma_dev_setup()
1237 pci_info(pdev, "Added to existing PE#%x\n", pe->pe_number); in pnv_pci_ioda_dma_dev_setup()
1244 if (!pe->dma_setup_done && !pci_is_bridge(pdev)) { in pnv_pci_ioda_dma_dev_setup()
1247 pnv_pci_ioda1_setup_dma_pe(phb, pe); in pnv_pci_ioda_dma_dev_setup()
1250 pnv_pci_ioda2_setup_dma_pe(phb, pe); in pnv_pci_ioda_dma_dev_setup()
1259 pdn->pe_number = pe->pe_number; in pnv_pci_ioda_dma_dev_setup()
1260 pe->device_count++; in pnv_pci_ioda_dma_dev_setup()
1263 pdev->dev.archdata.dma_offset = pe->tce_bypass_base; in pnv_pci_ioda_dma_dev_setup()
1264 set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); in pnv_pci_ioda_dma_dev_setup()
1267 if (pe->table_group.group) in pnv_pci_ioda_dma_dev_setup()
1268 iommu_add_device(&pe->table_group, &pdev->dev); in pnv_pci_ioda_dma_dev_setup()
1274 * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses.
1288 static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe) in pnv_pci_ioda_dma_64bit_bypass() argument
1307 table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL, in pnv_pci_ioda_dma_64bit_bypass()
1323 rc = opal_pci_map_pe_dma_window(pe->phb->opal_id, in pnv_pci_ioda_dma_64bit_bypass()
1324 pe->pe_number, in pnv_pci_ioda_dma_64bit_bypass()
1326 (pe->pe_number << 1) + 0, in pnv_pci_ioda_dma_64bit_bypass()
1332 pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n"); in pnv_pci_ioda_dma_64bit_bypass()
1336 pe_err(pe, "Error configuring 64-bit DMA bypass\n"); in pnv_pci_ioda_dma_64bit_bypass()
1345 struct pnv_ioda_pe *pe; in pnv_pci_ioda_iommu_bypass_supported() local
1350 pe = &phb->ioda.pe_array[pdn->pe_number]; in pnv_pci_ioda_iommu_bypass_supported()
1351 if (pe->tce_bypass_enabled) { in pnv_pci_ioda_iommu_bypass_supported()
1352 u64 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; in pnv_pci_ioda_iommu_bypass_supported()
1365 /* pe->pdev should be set if it's a single device, pe->pbus if not */ in pnv_pci_ioda_iommu_bypass_supported()
1366 (pe->device_count == 1 || !pe->pbus) && in pnv_pci_ioda_iommu_bypass_supported()
1369 s64 rc = pnv_pci_ioda_dma_64bit_bypass(pe); in pnv_pci_ioda_iommu_bypass_supported()
1393 struct pnv_ioda_pe *pe = container_of(tgl->table_group, in pnv_pci_p7ioc_tce_invalidate() local
1395 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); in pnv_pci_p7ioc_tce_invalidate()
1483 static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe) in pnv_pci_phb3_tce_invalidate_pe() argument
1485 /* 01xb - invalidate TCEs that match the specified PE# */ in pnv_pci_phb3_tce_invalidate_pe()
1486 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false); in pnv_pci_phb3_tce_invalidate_pe()
1487 unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); in pnv_pci_phb3_tce_invalidate_pe()
1493 static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm, in pnv_pci_phb3_tce_invalidate() argument
1497 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); in pnv_pci_phb3_tce_invalidate()
1500 /* We'll invalidate DMA address in PE scope */ in pnv_pci_phb3_tce_invalidate()
1502 start |= (pe->pe_number & 0xFF); in pnv_pci_phb3_tce_invalidate()
1520 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe) in pnv_pci_ioda2_tce_invalidate_pe() argument
1522 struct pnv_phb *phb = pe->phb; in pnv_pci_ioda2_tce_invalidate_pe()
1525 pnv_pci_phb3_tce_invalidate_pe(pe); in pnv_pci_ioda2_tce_invalidate_pe()
1528 pe->pe_number, 0, 0, 0); in pnv_pci_ioda2_tce_invalidate_pe()
1537 struct pnv_ioda_pe *pe = container_of(tgl->table_group, in pnv_pci_ioda2_tce_invalidate() local
1539 struct pnv_phb *phb = pe->phb; in pnv_pci_ioda2_tce_invalidate()
1557 pnv_pci_phb3_tce_invalidate(pe, rm, shift, in pnv_pci_ioda2_tce_invalidate()
1562 pe->pe_number, 1u << shift, in pnv_pci_ioda2_tce_invalidate()
1631 static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe) in pnv_pci_ioda_pe_dma_weight() argument
1637 if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) { in pnv_pci_ioda_pe_dma_weight()
1638 pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight); in pnv_pci_ioda_pe_dma_weight()
1643 if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) { in pnv_pci_ioda_pe_dma_weight()
1644 pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight); in pnv_pci_ioda_pe_dma_weight()
1645 } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) { in pnv_pci_ioda_pe_dma_weight()
1648 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) in pnv_pci_ioda_pe_dma_weight()
1650 } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) { in pnv_pci_ioda_pe_dma_weight()
1651 pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight); in pnv_pci_ioda_pe_dma_weight()
1658 struct pnv_ioda_pe *pe) in pnv_pci_ioda1_setup_dma_pe() argument
1671 weight = pnv_pci_ioda_pe_dma_weight(pe); in pnv_pci_ioda1_setup_dma_pe()
1701 pe_warn(pe, "No available DMA32 segments\n"); in pnv_pci_ioda1_setup_dma_pe()
1710 iommu_register_group(&pe->table_group, phb->hose->global_number, in pnv_pci_ioda1_setup_dma_pe()
1711 pe->pe_number); in pnv_pci_ioda1_setup_dma_pe()
1712 pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); in pnv_pci_ioda1_setup_dma_pe()
1715 pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n", in pnv_pci_ioda1_setup_dma_pe()
1717 pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", in pnv_pci_ioda1_setup_dma_pe()
1733 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); in pnv_pci_ioda1_setup_dma_pe()
1742 pe->pe_number, in pnv_pci_ioda1_setup_dma_pe()
1747 pe_err(pe, " Failed to configure 32-bit TCE table, err %lld\n", in pnv_pci_ioda1_setup_dma_pe()
1755 phb->ioda.dma32_segmap[i] = pe->pe_number; in pnv_pci_ioda1_setup_dma_pe()
1763 pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; in pnv_pci_ioda1_setup_dma_pe()
1764 pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; in pnv_pci_ioda1_setup_dma_pe()
1767 pe->dma_setup_done = true; in pnv_pci_ioda1_setup_dma_pe()
1774 pnv_pci_unlink_table_and_group(tbl, &pe->table_group); in pnv_pci_ioda1_setup_dma_pe()
1782 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, in pnv_pci_ioda2_set_window() local
1784 struct pnv_phb *phb = pe->phb; in pnv_pci_ioda2_set_window()
1791 pe_info(pe, "Setting up window#%d %llx..%llx pg=%lx\n", in pnv_pci_ioda2_set_window()
1796 * Map TCE table through TVT. The TVE index is the PE number in pnv_pci_ioda2_set_window()
1800 pe->pe_number, in pnv_pci_ioda2_set_window()
1801 (pe->pe_number << 1) + num, in pnv_pci_ioda2_set_window()
1807 pe_err(pe, "Failed to configure TCE table, err %lld\n", rc); in pnv_pci_ioda2_set_window()
1812 tbl, &pe->table_group); in pnv_pci_ioda2_set_window()
1813 pnv_pci_ioda2_tce_invalidate_pe(pe); in pnv_pci_ioda2_set_window()
1818 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) in pnv_pci_ioda2_set_bypass() argument
1820 uint16_t window_id = (pe->pe_number << 1 ) + 1; in pnv_pci_ioda2_set_bypass()
1823 pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); in pnv_pci_ioda2_set_bypass()
1828 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, in pnv_pci_ioda2_set_bypass()
1829 pe->pe_number, in pnv_pci_ioda2_set_bypass()
1831 pe->tce_bypass_base, in pnv_pci_ioda2_set_bypass()
1834 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, in pnv_pci_ioda2_set_bypass()
1835 pe->pe_number, in pnv_pci_ioda2_set_bypass()
1837 pe->tce_bypass_base, in pnv_pci_ioda2_set_bypass()
1841 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); in pnv_pci_ioda2_set_bypass()
1843 pe->tce_bypass_enabled = enable; in pnv_pci_ioda2_set_bypass()
1850 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, in pnv_pci_ioda2_create_table() local
1852 int nid = pe->phb->hose->node; in pnv_pci_ioda2_create_table()
1853 __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; in pnv_pci_ioda2_create_table()
1876 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) in pnv_pci_ioda2_setup_default_config() argument
1918 rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, PAGE_SHIFT, in pnv_pci_ioda2_setup_default_config()
1921 pe_err(pe, "Failed to create 32-bit TCE table, err %ld", in pnv_pci_ioda2_setup_default_config()
1929 if (window_size > pe->phb->ioda.m32_pci_base) { in pnv_pci_ioda2_setup_default_config()
1930 res_start = pe->phb->ioda.m32_pci_base >> tbl->it_page_shift; in pnv_pci_ioda2_setup_default_config()
1933 iommu_init_table(tbl, pe->phb->hose->node, res_start, res_end); in pnv_pci_ioda2_setup_default_config()
1935 rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); in pnv_pci_ioda2_setup_default_config()
1937 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", in pnv_pci_ioda2_setup_default_config()
1944 pnv_pci_ioda2_set_bypass(pe, true); in pnv_pci_ioda2_setup_default_config()
1951 if (pe->pdev) in pnv_pci_ioda2_setup_default_config()
1952 set_iommu_table_base(&pe->pdev->dev, tbl); in pnv_pci_ioda2_setup_default_config()
1960 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, in pnv_pci_ioda2_unset_window() local
1962 struct pnv_phb *phb = pe->phb; in pnv_pci_ioda2_unset_window()
1965 pe_info(pe, "Removing DMA window #%d\n", num); in pnv_pci_ioda2_unset_window()
1967 ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, in pnv_pci_ioda2_unset_window()
1968 (pe->pe_number << 1) + num, in pnv_pci_ioda2_unset_window()
1972 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); in pnv_pci_ioda2_unset_window()
1974 pnv_pci_ioda2_tce_invalidate_pe(pe); in pnv_pci_ioda2_unset_window()
2028 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus) in pnv_ioda_setup_bus_dma() argument
2033 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); in pnv_ioda_setup_bus_dma()
2034 dev->dev.archdata.dma_offset = pe->tce_bypass_base; in pnv_ioda_setup_bus_dma()
2036 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) in pnv_ioda_setup_bus_dma()
2037 pnv_ioda_setup_bus_dma(pe, dev->subordinate); in pnv_ioda_setup_bus_dma()
2043 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, in pnv_ioda2_take_ownership() local
2046 struct iommu_table *tbl = pe->table_group.tables[0]; in pnv_ioda2_take_ownership()
2048 pnv_pci_ioda2_set_bypass(pe, false); in pnv_ioda2_take_ownership()
2049 pnv_pci_ioda2_unset_window(&pe->table_group, 0); in pnv_ioda2_take_ownership()
2050 if (pe->pbus) in pnv_ioda2_take_ownership()
2051 pnv_ioda_setup_bus_dma(pe, pe->pbus); in pnv_ioda2_take_ownership()
2052 else if (pe->pdev) in pnv_ioda2_take_ownership()
2053 set_iommu_table_base(&pe->pdev->dev, NULL); in pnv_ioda2_take_ownership()
2059 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, in pnv_ioda2_release_ownership() local
2062 pnv_pci_ioda2_setup_default_config(pe); in pnv_ioda2_release_ownership()
2063 if (pe->pbus) in pnv_ioda2_release_ownership()
2064 pnv_ioda_setup_bus_dma(pe, pe->pbus); in pnv_ioda2_release_ownership()
2078 struct pnv_ioda_pe *pe) in pnv_pci_ioda2_setup_dma_pe() argument
2083 pe->tce_bypass_base = 1ull << 59; in pnv_pci_ioda2_setup_dma_pe()
2085 /* The PE will reserve all possible 32-bits space */ in pnv_pci_ioda2_setup_dma_pe()
2086 pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", in pnv_pci_ioda2_setup_dma_pe()
2090 pe->table_group.tce32_start = 0; in pnv_pci_ioda2_setup_dma_pe()
2091 pe->table_group.tce32_size = phb->ioda.m32_pci_base; in pnv_pci_ioda2_setup_dma_pe()
2092 pe->table_group.max_dynamic_windows_supported = in pnv_pci_ioda2_setup_dma_pe()
2094 pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; in pnv_pci_ioda2_setup_dma_pe()
2095 pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb); in pnv_pci_ioda2_setup_dma_pe()
2097 rc = pnv_pci_ioda2_setup_default_config(pe); in pnv_pci_ioda2_setup_dma_pe()
2102 pe->table_group.ops = &pnv_pci_ioda2_ops; in pnv_pci_ioda2_setup_dma_pe()
2103 iommu_register_group(&pe->table_group, phb->hose->global_number, in pnv_pci_ioda2_setup_dma_pe()
2104 pe->pe_number); in pnv_pci_ioda2_setup_dma_pe()
2106 pe->dma_setup_done = true; in pnv_pci_ioda2_setup_dma_pe()
2167 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); in pnv_pci_ioda_msi_setup() local
2172 /* No PE assigned ? bail out ... no MSI for you ! */ in pnv_pci_ioda_msi_setup()
2173 if (pe == NULL) in pnv_pci_ioda_msi_setup()
2177 if (pe->mve_number < 0) in pnv_pci_ioda_msi_setup()
2184 /* Assign XIVE to PE */ in pnv_pci_ioda_msi_setup()
2185 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); in pnv_pci_ioda_msi_setup()
2187 pr_warn("%s: OPAL error %d setting XIVE %d PE\n", in pnv_pci_ioda_msi_setup()
2195 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, in pnv_pci_ioda_msi_setup()
2207 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, in pnv_pci_ioda_msi_setup()
2222 " address=%x_%08x data=%x PE# %x\n", in pnv_pci_ioda_msi_setup()
2224 msg->address_hi, msg->address_lo, data, pe->pe_number); in pnv_pci_ioda_msi_setup()
2255 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, in pnv_ioda_setup_pe_res() argument
2258 struct pnv_phb *phb = pe->phb; in pnv_ioda_setup_pe_res()
2273 phb->ioda.io_segmap[index] = pe->pe_number; in pnv_ioda_setup_pe_res()
2275 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); in pnv_ioda_setup_pe_res()
2277 pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n", in pnv_ioda_setup_pe_res()
2278 __func__, rc, index, pe->pe_number); in pnv_ioda_setup_pe_res()
2297 phb->ioda.m32_segmap[index] = pe->pe_number; in pnv_ioda_setup_pe_res()
2299 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); in pnv_ioda_setup_pe_res()
2301 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x", in pnv_ioda_setup_pe_res()
2302 __func__, rc, index, pe->pe_number); in pnv_ioda_setup_pe_res()
2313 * This function is supposed to be called on basis of PE from top
2315 * parent PE could be overridden by its child PEs if necessary.
2317 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) in pnv_ioda_setup_pe_seg() argument
2323 * NOTE: We only care PCI bus based PE for now. For PCI in pnv_ioda_setup_pe_seg()
2324 * device based PE, for example SRIOV sensitive VF should in pnv_ioda_setup_pe_seg()
2327 BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); in pnv_ioda_setup_pe_seg()
2329 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { in pnv_ioda_setup_pe_seg()
2331 pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); in pnv_ioda_setup_pe_seg()
2334 * If the PE contains all subordinate PCI buses, the in pnv_ioda_setup_pe_seg()
2336 * the PE as well. in pnv_ioda_setup_pe_seg()
2338 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) in pnv_ioda_setup_pe_seg()
2341 pnv_ioda_setup_pe_res(pe, in pnv_ioda_setup_pe_seg()
2372 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_num]; in pnv_pci_ioda_pe_dump() local
2377 pe_warn(pe, "rid: %04x dev count: %2d flags: %s%s%s%s%s%s\n", in pnv_pci_ioda_pe_dump()
2378 pe->rid, pe->device_count, in pnv_pci_ioda_pe_dump()
2379 (pe->flags & PNV_IODA_PE_DEV) ? "dev " : "", in pnv_pci_ioda_pe_dump()
2380 (pe->flags & PNV_IODA_PE_BUS) ? "bus " : "", in pnv_pci_ioda_pe_dump()
2381 (pe->flags & PNV_IODA_PE_BUS_ALL) ? "all " : "", in pnv_pci_ioda_pe_dump()
2382 (pe->flags & PNV_IODA_PE_MASTER) ? "master " : "", in pnv_pci_ioda_pe_dump()
2383 (pe->flags & PNV_IODA_PE_SLAVE) ? "slave " : "", in pnv_pci_ioda_pe_dump()
2384 (pe->flags & PNV_IODA_PE_VF) ? "vf " : ""); in pnv_pci_ioda_pe_dump()
2469 * For now, we return I/O or M32 segment size for PE sensitive
2473 * The current PCI bus might be put into one PE, which was
2570 struct pnv_ioda_pe *pe; in pnv_pci_configure_bus() local
2573 dev_info(&bus->dev, "Configuring PE for bus\n"); in pnv_pci_configure_bus()
2575 /* Don't assign PE to PCI bus, which doesn't have subordinate devices */ in pnv_pci_configure_bus()
2583 * Assign PE. We might run here because of partial hotplug. in pnv_pci_configure_bus()
2584 * For the case, we just pick up the existing PE and should in pnv_pci_configure_bus()
2587 pe = pnv_ioda_setup_bus_PE(bus, all); in pnv_pci_configure_bus()
2588 if (!pe) in pnv_pci_configure_bus()
2591 pnv_ioda_setup_pe_seg(pe); in pnv_pci_configure_bus()
2600 * assign a PE
2627 struct pnv_ioda_pe *pe; in pnv_ocapi_enable_device_hook() local
2637 pe = pnv_ioda_setup_dev_PE(dev); in pnv_ocapi_enable_device_hook()
2638 if (!pe) in pnv_ocapi_enable_device_hook()
2647 struct pnv_ioda_pe *pe = container_of(table_group, in pnv_pci_ioda1_unset_window() local
2649 struct pnv_phb *phb = pe->phb; in pnv_pci_ioda1_unset_window()
2653 pe_info(pe, "Removing DMA window #%d\n", num); in pnv_pci_ioda1_unset_window()
2655 if (phb->ioda.dma32_segmap[idx] != pe->pe_number) in pnv_pci_ioda1_unset_window()
2658 rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, in pnv_pci_ioda1_unset_window()
2661 pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n", in pnv_pci_ioda1_unset_window()
2673 static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe) in pnv_pci_ioda1_release_pe_dma() argument
2675 struct iommu_table *tbl = pe->table_group.tables[0]; in pnv_pci_ioda1_release_pe_dma()
2678 if (!pe->dma_setup_done) in pnv_pci_ioda1_release_pe_dma()
2681 rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0); in pnv_pci_ioda1_release_pe_dma()
2686 if (pe->table_group.group) { in pnv_pci_ioda1_release_pe_dma()
2687 iommu_group_put(pe->table_group.group); in pnv_pci_ioda1_release_pe_dma()
2688 WARN_ON(pe->table_group.group); in pnv_pci_ioda1_release_pe_dma()
2695 void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe) in pnv_pci_ioda2_release_pe_dma() argument
2697 struct iommu_table *tbl = pe->table_group.tables[0]; in pnv_pci_ioda2_release_pe_dma()
2700 if (!pe->dma_setup_done) in pnv_pci_ioda2_release_pe_dma()
2703 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); in pnv_pci_ioda2_release_pe_dma()
2705 pe_warn(pe, "OPAL error %lld release DMA window\n", rc); in pnv_pci_ioda2_release_pe_dma()
2707 pnv_pci_ioda2_set_bypass(pe, false); in pnv_pci_ioda2_release_pe_dma()
2708 if (pe->table_group.group) { in pnv_pci_ioda2_release_pe_dma()
2709 iommu_group_put(pe->table_group.group); in pnv_pci_ioda2_release_pe_dma()
2710 WARN_ON(pe->table_group.group); in pnv_pci_ioda2_release_pe_dma()
2716 static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe, in pnv_ioda_free_pe_seg() argument
2720 struct pnv_phb *phb = pe->phb; in pnv_ioda_free_pe_seg()
2725 if (map[idx] != pe->pe_number) in pnv_ioda_free_pe_seg()
2732 pe_warn(pe, "Error %lld unmapping (%d) segment#%d\n", in pnv_ioda_free_pe_seg()
2739 static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe) in pnv_ioda_release_pe_seg() argument
2741 struct pnv_phb *phb = pe->phb; in pnv_ioda_release_pe_seg()
2744 pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE, in pnv_ioda_release_pe_seg()
2746 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, in pnv_ioda_release_pe_seg()
2750 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, in pnv_ioda_release_pe_seg()
2755 static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe) in pnv_ioda_release_pe() argument
2757 struct pnv_phb *phb = pe->phb; in pnv_ioda_release_pe()
2760 pe_info(pe, "Releasing PE\n"); in pnv_ioda_release_pe()
2763 list_del(&pe->list); in pnv_ioda_release_pe()
2768 pnv_pci_ioda1_release_pe_dma(pe); in pnv_ioda_release_pe()
2771 pnv_pci_ioda2_release_pe_dma(pe); in pnv_ioda_release_pe()
2779 pnv_ioda_release_pe_seg(pe); in pnv_ioda_release_pe()
2780 pnv_ioda_deconfigure_pe(pe->phb, pe); in pnv_ioda_release_pe()
2782 /* Release slave PEs in the compound PE */ in pnv_ioda_release_pe()
2783 if (pe->flags & PNV_IODA_PE_MASTER) { in pnv_ioda_release_pe()
2784 list_for_each_entry_safe(slave, tmp, &pe->slaves, list) { in pnv_ioda_release_pe()
2791 * The PE for root bus can be removed because of hotplug in EEH in pnv_ioda_release_pe()
2792 * recovery for fenced PHB error. We need to mark the PE dead so in pnv_ioda_release_pe()
2793 * that it can be populated again in PCI hot add path. The PE in pnv_ioda_release_pe()
2796 if (phb->ioda.root_pe_idx == pe->pe_number) in pnv_ioda_release_pe()
2799 pnv_ioda_free_pe(pe); in pnv_ioda_release_pe()
2806 struct pnv_ioda_pe *pe; in pnv_pci_release_device() local
2808 /* The VF PE state is torn down when sriov_disable() is called */ in pnv_pci_release_device()
2828 * set the PE number in @pdn to an invalid one. Otherwise, the PE's in pnv_pci_release_device()
2830 * be increased on adding devices. It leads to unbalanced PE's device in pnv_pci_release_device()
2833 pe = &phb->ioda.pe_array[pdn->pe_number]; in pnv_pci_release_device()
2836 WARN_ON(--pe->device_count < 0); in pnv_pci_release_device()
2837 if (pe->device_count == 0) in pnv_pci_release_device()
2838 pnv_ioda_release_pe(pe); in pnv_pci_release_device()
2844 struct eeh_pe *eehpe = edev ? edev->pe : NULL; in pnv_npu_disable_device()
2861 struct pnv_ioda_pe *pe; in pnv_pci_ioda_dma_bus_setup() local
2863 list_for_each_entry(pe, &phb->ioda.pe_list, list) { in pnv_pci_ioda_dma_bus_setup()
2864 if (!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))) in pnv_pci_ioda_dma_bus_setup()
2867 if (!pe->pbus) in pnv_pci_ioda_dma_bus_setup()
2870 if (bus->number == ((pe->rid >> 8) & 0xFF)) { in pnv_pci_ioda_dma_bus_setup()
2871 pe->pbus = bus; in pnv_pci_ioda_dma_bus_setup()
3009 prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); in pnv_pci_init_ioda_phb()
3013 /* Invalidate RID to PE# mapping */ in pnv_pci_init_ioda_phb()
3072 * Choose PE number for root bus, which shouldn't have in pnv_pci_init_ioda_phb()
3074 * the PE number adjacent to the reserved one if possible. in pnv_pci_init_ioda_phb()
3105 pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", in pnv_pci_init_ioda_phb()
3129 * the child P2P bridges) can form individual PE. in pnv_pci_init_ioda_phb()