Lines Matching +full:max +full:- +full:outbound +full:- +full:regions
2 * PCI / PCI-X / PCI-Express support for 4xx parts
29 #include <asm/pci-bridge.h>
32 #include <asm/dcr-regs.h>
61 if (dev->devfn != 0 || dev->bus->self != NULL) in fixup_ppc4xx_pci_bridge()
64 hose = pci_bus_to_host(dev->bus); in fixup_ppc4xx_pci_bridge()
68 if (!of_device_is_compatible(hose->dn, "ibm,plb-pciex") && in fixup_ppc4xx_pci_bridge()
69 !of_device_is_compatible(hose->dn, "ibm,plb-pcix") && in fixup_ppc4xx_pci_bridge()
70 !of_device_is_compatible(hose->dn, "ibm,plb-pci")) in fixup_ppc4xx_pci_bridge()
73 if (of_device_is_compatible(hose->dn, "ibm,plb440epx-pci") || in fixup_ppc4xx_pci_bridge()
74 of_device_is_compatible(hose->dn, "ibm,plb440grx-pci")) { in fixup_ppc4xx_pci_bridge()
75 hose->indirect_type |= PPC_INDIRECT_TYPE_BROKEN_MRM; in fixup_ppc4xx_pci_bridge()
82 dev->resource[i].start = dev->resource[i].end = 0; in fixup_ppc4xx_pci_bridge()
83 dev->resource[i].flags = 0; in fixup_ppc4xx_pci_bridge()
98 int pna = of_n_addr_cells(hose->dn); in ppc4xx_parse_dma_ranges()
102 res->start = 0; in ppc4xx_parse_dma_ranges()
104 res->end = size - 1; in ppc4xx_parse_dma_ranges()
105 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; in ppc4xx_parse_dma_ranges()
107 /* Get dma-ranges property */ in ppc4xx_parse_dma_ranges()
108 ranges = of_get_property(hose->dn, "dma-ranges", &rlen); in ppc4xx_parse_dma_ranges()
113 while ((rlen -= np * 4) >= 0) { in ppc4xx_parse_dma_ranges()
116 u64 cpu_addr = of_translate_dma_address(hose->dn, ranges + 3); in ppc4xx_parse_dma_ranges()
131 " 0x%016llx...0x%016llx -> 0x%016llx\n", in ppc4xx_parse_dma_ranges()
132 hose->dn, in ppc4xx_parse_dma_ranges()
133 pci_addr, pci_addr + size - 1, cpu_addr); in ppc4xx_parse_dma_ranges()
139 res->flags &= ~IORESOURCE_PREFETCH; in ppc4xx_parse_dma_ranges()
143 res->start = pci_addr; in ppc4xx_parse_dma_ranges()
147 res->end = 0xffffffff; in ppc4xx_parse_dma_ranges()
149 res->end = res->start + size - 1; in ppc4xx_parse_dma_ranges()
154 if (dma_offset_set && pci_dram_offset != res->start) { in ppc4xx_parse_dma_ranges()
155 printk(KERN_ERR "%pOF: dma-ranges(s) mismatch\n", hose->dn); in ppc4xx_parse_dma_ranges()
156 return -ENXIO; in ppc4xx_parse_dma_ranges()
163 printk(KERN_ERR "%pOF: dma-ranges too small " in ppc4xx_parse_dma_ranges()
165 hose->dn, size, (u64)total_memory); in ppc4xx_parse_dma_ranges()
166 return -ENXIO; in ppc4xx_parse_dma_ranges()
170 if ((size & (size - 1)) != 0 || in ppc4xx_parse_dma_ranges()
171 (res->start & (size - 1)) != 0) { in ppc4xx_parse_dma_ranges()
172 printk(KERN_ERR "%pOF: dma-ranges unaligned\n", hose->dn); in ppc4xx_parse_dma_ranges()
173 return -ENXIO; in ppc4xx_parse_dma_ranges()
179 if (res->end > 0xffffffff && in ppc4xx_parse_dma_ranges()
180 !(of_device_is_compatible(hose->dn, "ibm,plb-pciex-460sx") in ppc4xx_parse_dma_ranges()
181 || of_device_is_compatible(hose->dn, "ibm,plb-pciex-476fpe"))) { in ppc4xx_parse_dma_ranges()
182 printk(KERN_ERR "%pOF: dma-ranges outside of 32 bits space\n", in ppc4xx_parse_dma_ranges()
183 hose->dn); in ppc4xx_parse_dma_ranges()
184 return -ENXIO; in ppc4xx_parse_dma_ranges()
188 pci_dram_offset = res->start; in ppc4xx_parse_dma_ranges()
189 hose->dma_window_base_cur = res->start; in ppc4xx_parse_dma_ranges()
190 hose->dma_window_size = resource_size(res); in ppc4xx_parse_dma_ranges()
195 (unsigned long long)hose->dma_window_base_cur); in ppc4xx_parse_dma_ranges()
197 (unsigned long long)hose->dma_window_size); in ppc4xx_parse_dma_ranges()
216 * 32-bit of incoming PLB addresses. The top 4 bits of the 36-bit in ppc4xx_setup_one_pci_PMM()
221 * programming the chip. That means the device-tree has to be right in ppc4xx_setup_one_pci_PMM()
233 size < 0x1000 || (plb_addr & (size - 1)) != 0) { in ppc4xx_setup_one_pci_PMM()
234 printk(KERN_WARNING "%pOF: Resource out of range\n", hose->dn); in ppc4xx_setup_one_pci_PMM()
235 return -1; in ppc4xx_setup_one_pci_PMM()
257 /* Setup outbound memory windows */ in ppc4xx_configure_pci_PMMs()
259 struct resource *res = &hose->mem_resources[i]; in ppc4xx_configure_pci_PMMs()
260 resource_size_t offset = hose->mem_offset[i]; in ppc4xx_configure_pci_PMMs()
263 if (!(res->flags & IORESOURCE_MEM)) in ppc4xx_configure_pci_PMMs()
266 printk(KERN_WARNING "%pOF: Too many ranges\n", hose->dn); in ppc4xx_configure_pci_PMMs()
272 res->start, in ppc4xx_configure_pci_PMMs()
273 res->start - offset, in ppc4xx_configure_pci_PMMs()
275 res->flags, in ppc4xx_configure_pci_PMMs()
282 if (res->start == offset) in ppc4xx_configure_pci_PMMs()
288 if (j <= 2 && !found_isa_hole && hose->isa_mem_size) in ppc4xx_configure_pci_PMMs()
289 if (ppc4xx_setup_one_pci_PMM(hose, reg, hose->isa_mem_phys, 0, in ppc4xx_configure_pci_PMMs()
290 hose->isa_mem_size, 0, j) == 0) in ppc4xx_configure_pci_PMMs()
292 hose->dn); in ppc4xx_configure_pci_PMMs()
311 early_write_config_dword(hose, hose->first_busno, 0, in ppc4xx_configure_pci_PTMs()
312 PCI_BASE_ADDRESS_1, res->start); in ppc4xx_configure_pci_PTMs()
313 early_write_config_dword(hose, hose->first_busno, 0, in ppc4xx_configure_pci_PTMs()
315 early_write_config_word(hose, hose->first_busno, 0, in ppc4xx_configure_pci_PTMs()
332 printk(KERN_INFO "%pOF: Port disabled via device-tree\n", np); in ppc4xx_probe_pci_bridge()
354 bus_range = of_get_property(np, "bus-range", NULL); in ppc4xx_probe_pci_bridge()
368 hose->first_busno = bus_range ? bus_range[0] : 0x0; in ppc4xx_probe_pci_bridge()
369 hose->last_busno = bus_range ? bus_range[1] : 0xff; in ppc4xx_probe_pci_bridge()
381 /* Parse outbound mapping resources */ in ppc4xx_probe_pci_bridge()
388 /* Configure outbound ranges POMs */ in ppc4xx_probe_pci_bridge()
406 * 4xx PCI-X part
420 (plb_addr & (size - 1)) != 0) { in ppc4xx_setup_one_pcix_POM()
422 hose->dn); in ppc4xx_setup_one_pcix_POM()
423 return -1; in ppc4xx_setup_one_pcix_POM()
456 /* Setup outbound memory windows */ in ppc4xx_configure_pcix_POMs()
458 struct resource *res = &hose->mem_resources[i]; in ppc4xx_configure_pcix_POMs()
459 resource_size_t offset = hose->mem_offset[i]; in ppc4xx_configure_pcix_POMs()
462 if (!(res->flags & IORESOURCE_MEM)) in ppc4xx_configure_pcix_POMs()
465 printk(KERN_WARNING "%pOF: Too many ranges\n", hose->dn); in ppc4xx_configure_pcix_POMs()
471 res->start, in ppc4xx_configure_pcix_POMs()
472 res->start - offset, in ppc4xx_configure_pcix_POMs()
474 res->flags, in ppc4xx_configure_pcix_POMs()
481 if (res->start == offset) in ppc4xx_configure_pcix_POMs()
487 if (j <= 1 && !found_isa_hole && hose->isa_mem_size) in ppc4xx_configure_pcix_POMs()
488 if (ppc4xx_setup_one_pcix_POM(hose, reg, hose->isa_mem_phys, 0, in ppc4xx_configure_pcix_POMs()
489 hose->isa_mem_size, 0, j) == 0) in ppc4xx_configure_pcix_POMs()
491 hose->dn); in ppc4xx_configure_pcix_POMs()
510 if (res->flags & IORESOURCE_PREFETCH) in ppc4xx_configure_pcix_PIMs()
520 writel(res->start, reg + PCIX0_BAR0L); in ppc4xx_configure_pcix_PIMs()
536 printk(KERN_ERR "%pOF: Can't get PCI-X config register base !", in ppc4xx_probe_pcix_bridge()
542 printk(KERN_ERR "%pOF: Can't get PCI-X internal register base !", in ppc4xx_probe_pcix_bridge()
548 if (of_get_property(np, "large-inbound-windows", NULL)) in ppc4xx_probe_pcix_bridge()
552 if (of_get_property(np, "enable-msi-hole", NULL)) in ppc4xx_probe_pcix_bridge()
560 bus_range = of_get_property(np, "bus-range", NULL); in ppc4xx_probe_pcix_bridge()
574 hose->first_busno = bus_range ? bus_range[0] : 0x0; in ppc4xx_probe_pcix_bridge()
575 hose->last_busno = bus_range ? bus_range[1] : 0xff; in ppc4xx_probe_pcix_bridge()
593 /* Parse outbound mapping resources */ in ppc4xx_probe_pcix_bridge()
600 /* Configure outbound ranges POMs */ in ppc4xx_probe_pcix_bridge()
620 * 4xx PCI-Express part
624 * ibm,plb-pciex-440spe
625 * ibm,plb-pciex-405ex
626 * ibm,plb-pciex-460ex
672 while(timeout_ms--) { in ppc4xx_pciex_wait_on_sdr()
673 val = mfdcri(SDR0, port->sdr_base + sdr_offset); in ppc4xx_pciex_wait_on_sdr()
676 port->index, sdr_offset, timeout_ms, val); in ppc4xx_pciex_wait_on_sdr()
681 return -1; in ppc4xx_pciex_wait_on_sdr()
689 port->index); in ppc4xx_pciex_port_reset_sdr()
690 return -1; in ppc4xx_pciex_port_reset_sdr()
698 printk(KERN_INFO "PCIE%d: Checking link...\n", port->index); in ppc4xx_pciex_check_link_sdr()
707 if (!port->has_ibpre || in ppc4xx_pciex_check_link_sdr()
712 port->index); in ppc4xx_pciex_check_link_sdr()
716 "PCIE%d: Link up failed\n", port->index); in ppc4xx_pciex_check_link_sdr()
719 "PCIE%d: link is up !\n", port->index); in ppc4xx_pciex_check_link_sdr()
720 port->link = 1; in ppc4xx_pciex_check_link_sdr()
723 printk(KERN_INFO "PCIE%d: No device detected.\n", port->index); in ppc4xx_pciex_check_link_sdr()
738 * by firmware - let's re-reset RCSSET regs in ppc440spe_pciex_check_reset()
740 * -- Shouldn't we also re-reset the whole thing ? -- BenH in ppc440spe_pciex_check_reset()
757 err = -1; in ppc440spe_pciex_check_reset()
765 err = -1; in ppc440spe_pciex_check_reset()
773 err = -1; in ppc440spe_pciex_check_reset()
781 err = -1; in ppc440spe_pciex_check_reset()
789 err = -1; in ppc440spe_pciex_check_reset()
797 err = -1; in ppc440spe_pciex_check_reset()
813 return -ENXIO; in ppc440spe_pciex_core_init()
819 return -1; in ppc440spe_pciex_core_init()
822 /* De-assert reset of PCIe PLL, wait for lock */ in ppc440spe_pciex_core_init()
828 time_out--; in ppc440spe_pciex_core_init()
835 return -1; in ppc440spe_pciex_core_init()
847 if (port->endpoint) in ppc440spe_pciex_init_port_hw()
852 if (port->index == 0) in ppc440spe_pciex_init_port_hw()
857 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val); in ppc440spe_pciex_init_port_hw()
858 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x20222222); in ppc440spe_pciex_init_port_hw()
860 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x11000000); in ppc440spe_pciex_init_port_hw()
861 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL0SET1, 0x35000000); in ppc440spe_pciex_init_port_hw()
862 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL1SET1, 0x35000000); in ppc440spe_pciex_init_port_hw()
863 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL2SET1, 0x35000000); in ppc440spe_pciex_init_port_hw()
864 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL3SET1, 0x35000000); in ppc440spe_pciex_init_port_hw()
865 if (port->index == 0) { in ppc440spe_pciex_init_port_hw()
866 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL4SET1, in ppc440spe_pciex_init_port_hw()
868 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL5SET1, in ppc440spe_pciex_init_port_hw()
870 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL6SET1, in ppc440spe_pciex_init_port_hw()
872 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1, in ppc440spe_pciex_init_port_hw()
875 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, in ppc440spe_pciex_init_port_hw()
890 port->has_ibpre = 1; in ppc440speB_pciex_init_port_hw()
898 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x68782800); in ppc440speA_pciex_init_utl()
903 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000); in ppc440speA_pciex_init_utl()
904 out_be32(port->utl_base + PEUTL_INTR, 0x02000000); in ppc440speA_pciex_init_utl()
905 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x10000000); in ppc440speA_pciex_init_utl()
906 out_be32(port->utl_base + PEUTL_PBBSZ, 0x53000000); in ppc440speA_pciex_init_utl()
907 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x08000000); in ppc440speA_pciex_init_utl()
908 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x10000000); in ppc440speA_pciex_init_utl()
909 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000); in ppc440speA_pciex_init_utl()
910 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066); in ppc440speA_pciex_init_utl()
918 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000); in ppc440speB_pciex_init_utl()
952 if (port->endpoint) in ppc460ex_pciex_init_port_hw()
957 if (port->index == 0) { in ppc460ex_pciex_init_port_hw()
965 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val); in ppc460ex_pciex_init_port_hw()
966 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, utlset1); in ppc460ex_pciex_init_port_hw()
967 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01210000); in ppc460ex_pciex_init_port_hw()
969 switch (port->index) { in ppc460ex_pciex_init_port_hw()
996 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, in ppc460ex_pciex_init_port_hw()
997 mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) | in ppc460ex_pciex_init_port_hw()
1002 switch (port->index) { in ppc460ex_pciex_init_port_hw()
1013 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, in ppc460ex_pciex_init_port_hw()
1014 (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) & in ppc460ex_pciex_init_port_hw()
1018 port->has_ibpre = 1; in ppc460ex_pciex_init_port_hw()
1025 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0); in ppc460ex_pciex_init_utl()
1030 out_be32(port->utl_base + PEUTL_PBCTL, 0x0800000c); in ppc460ex_pciex_init_utl()
1031 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000); in ppc460ex_pciex_init_utl()
1032 out_be32(port->utl_base + PEUTL_INTR, 0x02000000); in ppc460ex_pciex_init_utl()
1033 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000); in ppc460ex_pciex_init_utl()
1034 out_be32(port->utl_base + PEUTL_PBBSZ, 0x00000000); in ppc460ex_pciex_init_utl()
1035 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000); in ppc460ex_pciex_init_utl()
1036 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000); in ppc460ex_pciex_init_utl()
1037 out_be32(port->utl_base + PEUTL_RCIRQEN,0x00f00000); in ppc460ex_pciex_init_utl()
1038 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066); in ppc460ex_pciex_init_utl()
1064 * This code is to fix the issue that pci drivers doesn't re-assign in apm821xx_pciex_init_port_hw()
1073 if (port->endpoint) in apm821xx_pciex_init_port_hw()
1080 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val); in apm821xx_pciex_init_port_hw()
1081 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000); in apm821xx_pciex_init_port_hw()
1082 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000); in apm821xx_pciex_init_port_hw()
1092 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, in apm821xx_pciex_init_port_hw()
1093 mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) | in apm821xx_pciex_init_port_hw()
1097 val = PESDR0_460EX_RSTSTA - port->sdr_base; in apm821xx_pciex_init_port_hw()
1100 return -EBUSY; in apm821xx_pciex_init_port_hw()
1102 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, in apm821xx_pciex_init_port_hw()
1103 (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) & in apm821xx_pciex_init_port_hw()
1107 port->has_ibpre = 1; in apm821xx_pciex_init_port_hw()
1142 /* HSS TX pre-emphasis */ in ppc460sx_pciex_core_init()
1178 /* De-assert PLLRESET */ in ppc460sx_pciex_core_init()
1192 * If bifurcation is not enabled, u-boot would have disabled the in ppc460sx_pciex_core_init()
1209 if (port->endpoint) in ppc460sx_pciex_init_port_hw()
1210 dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2, in ppc460sx_pciex_init_port_hw()
1213 dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2, in ppc460sx_pciex_init_port_hw()
1216 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, in ppc460sx_pciex_init_port_hw()
1220 port->has_ibpre = 1; in ppc460sx_pciex_init_port_hw()
1227 /* Max 128 Bytes */ in ppc460sx_pciex_init_utl()
1228 out_be32 (port->utl_base + PEUTL_PBBSZ, 0x00000000); in ppc460sx_pciex_init_utl()
1229 /* Assert VRB and TXE - per datasheet turn off addr validation */ in ppc460sx_pciex_init_utl()
1230 out_be32(port->utl_base + PEUTL_PCTL, 0x80800000); in ppc460sx_pciex_init_utl()
1239 port->link = 0; in ppc460sx_pciex_check_link()
1241 mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000); in ppc460sx_pciex_check_link()
1244 port->node); in ppc460sx_pciex_check_link()
1250 attempt--; in ppc460sx_pciex_check_link()
1254 port->link = 1; in ppc460sx_pciex_check_link()
1279 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01010000); in ppc405ex_pcie_phy_reset()
1283 if (port->endpoint) in ppc405ex_pcie_phy_reset()
1284 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01111000); in ppc405ex_pcie_phy_reset()
1286 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01101000); in ppc405ex_pcie_phy_reset()
1290 while (!(mfdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSTA) & 0x00001000)) in ppc405ex_pcie_phy_reset()
1294 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x00101000); in ppc405ex_pcie_phy_reset()
1301 if (port->endpoint) in ppc405ex_pciex_init_port_hw()
1306 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, in ppc405ex_pciex_init_port_hw()
1309 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000); in ppc405ex_pciex_init_port_hw()
1310 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000); in ppc405ex_pciex_init_port_hw()
1311 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET1, 0x720F0000); in ppc405ex_pciex_init_port_hw()
1312 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET2, 0x70600003); in ppc405ex_pciex_init_port_hw()
1319 * This has to be re-tested and fixed in a later release! in ppc405ex_pciex_init_port_hw()
1321 val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP); in ppc405ex_pciex_init_port_hw()
1325 dcr_write(port->dcrs, DCRO_PEGPL_CFG, 0x10000000); /* guarded on */ in ppc405ex_pciex_init_port_hw()
1327 port->has_ibpre = 1; in ppc405ex_pciex_init_port_hw()
1334 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0); in ppc405ex_pciex_init_utl()
1339 out_be32(port->utl_base + PEUTL_OUTTR, 0x02000000); in ppc405ex_pciex_init_utl()
1340 out_be32(port->utl_base + PEUTL_INTR, 0x02000000); in ppc405ex_pciex_init_utl()
1341 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000); in ppc405ex_pciex_init_utl()
1342 out_be32(port->utl_base + PEUTL_PBBSZ, 0x21000000); in ppc405ex_pciex_init_utl()
1343 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000); in ppc405ex_pciex_init_utl()
1344 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000); in ppc405ex_pciex_init_utl()
1345 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000); in ppc405ex_pciex_init_utl()
1346 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066); in ppc405ex_pciex_init_utl()
1348 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000); in ppc405ex_pciex_init_utl()
1374 void __iomem *mbase = ioremap(port->cfg_space.start + 0x10000000, in ppc_476fpe_pciex_check_link()
1377 printk(KERN_INFO "PCIE%d: Checking link...\n", port->index); in ppc_476fpe_pciex_check_link()
1381 port->index); in ppc_476fpe_pciex_check_link()
1385 while (timeout_ms--) { in ppc_476fpe_pciex_check_link()
1394 printk(KERN_INFO "PCIE%d: link is up !\n", port->index); in ppc_476fpe_pciex_check_link()
1395 port->link = 1; in ppc_476fpe_pciex_check_link()
1397 printk(KERN_WARNING "PCIE%d: Link up failed\n", port->index); in ppc_476fpe_pciex_check_link()
1413 int count = -ENODEV; in ppc4xx_pciex_check_core_init()
1419 if (of_device_is_compatible(np, "ibm,plb-pciex-440spe")) { in ppc4xx_pciex_check_core_init()
1425 if (of_device_is_compatible(np, "ibm,plb-pciex-460ex")) in ppc4xx_pciex_check_core_init()
1427 if (of_device_is_compatible(np, "ibm,plb-pciex-460sx")) in ppc4xx_pciex_check_core_init()
1429 if (of_device_is_compatible(np, "ibm,plb-pciex-apm821xx")) in ppc4xx_pciex_check_core_init()
1433 if (of_device_is_compatible(np, "ibm,plb-pciex-405ex")) in ppc4xx_pciex_check_core_init()
1437 if (of_device_is_compatible(np, "ibm,plb-pciex-476fpe") in ppc4xx_pciex_check_core_init()
1438 || of_device_is_compatible(np, "ibm,plb-pciex-476gtr")) in ppc4xx_pciex_check_core_init()
1443 return -ENODEV; in ppc4xx_pciex_check_core_init()
1446 count = ppc4xx_pciex_hwops->core_init(np); in ppc4xx_pciex_check_core_init()
1456 return -ENOMEM; in ppc4xx_pciex_check_core_init()
1458 return -ENODEV; in ppc4xx_pciex_check_core_init()
1464 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAH, in ppc4xx_pciex_port_init_mapping()
1465 RES_TO_U32_HIGH(port->cfg_space.start)); in ppc4xx_pciex_port_init_mapping()
1466 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAL, in ppc4xx_pciex_port_init_mapping()
1467 RES_TO_U32_LOW(port->cfg_space.start)); in ppc4xx_pciex_port_init_mapping()
1470 dcr_write(port->dcrs, DCRO_PEGPL_CFGMSK, 0xe0000001); in ppc4xx_pciex_port_init_mapping()
1473 dcr_write(port->dcrs, DCRO_PEGPL_REGBAH, in ppc4xx_pciex_port_init_mapping()
1474 RES_TO_U32_HIGH(port->utl_regs.start)); in ppc4xx_pciex_port_init_mapping()
1475 dcr_write(port->dcrs, DCRO_PEGPL_REGBAL, in ppc4xx_pciex_port_init_mapping()
1476 RES_TO_U32_LOW(port->utl_regs.start)); in ppc4xx_pciex_port_init_mapping()
1479 dcr_write(port->dcrs, DCRO_PEGPL_REGMSK, 0x00007001); in ppc4xx_pciex_port_init_mapping()
1481 /* Disable all other outbound windows */ in ppc4xx_pciex_port_init_mapping()
1482 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, 0); in ppc4xx_pciex_port_init_mapping()
1483 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, 0); in ppc4xx_pciex_port_init_mapping()
1484 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, 0); in ppc4xx_pciex_port_init_mapping()
1485 dcr_write(port->dcrs, DCRO_PEGPL_MSGMSK, 0); in ppc4xx_pciex_port_init_mapping()
1493 if (ppc4xx_pciex_hwops->port_init_hw) in ppc4xx_pciex_port_init()
1494 rc = ppc4xx_pciex_hwops->port_init_hw(port); in ppc4xx_pciex_port_init()
1499 * Initialize mapping: disable all regions and configure in ppc4xx_pciex_port_init()
1500 * CFG and REG regions based on resources in the device tree in ppc4xx_pciex_port_init()
1504 if (ppc4xx_pciex_hwops->check_link) in ppc4xx_pciex_port_init()
1505 ppc4xx_pciex_hwops->check_link(port); in ppc4xx_pciex_port_init()
1510 port->utl_base = ioremap(port->utl_regs.start, 0x100); in ppc4xx_pciex_port_init()
1511 BUG_ON(port->utl_base == NULL); in ppc4xx_pciex_port_init()
1514 * Setup UTL registers --BenH. in ppc4xx_pciex_port_init()
1516 if (ppc4xx_pciex_hwops->setup_utl) in ppc4xx_pciex_port_init()
1517 ppc4xx_pciex_hwops->setup_utl(port); in ppc4xx_pciex_port_init()
1522 if (port->sdr_base) { in ppc4xx_pciex_port_init()
1523 if (of_device_is_compatible(port->node, in ppc4xx_pciex_port_init()
1524 "ibm,plb-pciex-460sx")){ in ppc4xx_pciex_port_init()
1525 if (port->link && ppc4xx_pciex_wait_on_sdr(port, in ppc4xx_pciex_port_init()
1529 port->index); in ppc4xx_pciex_port_init()
1530 port->link = 0; in ppc4xx_pciex_port_init()
1532 } else if (port->link && in ppc4xx_pciex_port_init()
1536 port->index); in ppc4xx_pciex_port_init()
1537 port->link = 0; in ppc4xx_pciex_port_init()
1540 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20); in ppc4xx_pciex_port_init()
1555 if (port->endpoint && bus->number != port->hose->first_busno) in ppc4xx_pciex_validate_bdf()
1559 if (bus->number > port->hose->last_busno) { in ppc4xx_pciex_validate_bdf()
1562 " out of range !\n", bus->number); in ppc4xx_pciex_validate_bdf()
1569 if (bus->number == port->hose->first_busno && devfn != 0) in ppc4xx_pciex_validate_bdf()
1573 if (bus->number == (port->hose->first_busno + 1) && in ppc4xx_pciex_validate_bdf()
1578 if ((bus->number != port->hose->first_busno) && !port->link) in ppc4xx_pciex_validate_bdf()
1593 if (bus->number == port->hose->first_busno) in ppc4xx_pciex_get_config_base()
1594 return (void __iomem *)port->hose->cfg_addr; in ppc4xx_pciex_get_config_base()
1596 relbus = bus->number - (port->hose->first_busno + 1); in ppc4xx_pciex_get_config_base()
1597 return (void __iomem *)port->hose->cfg_data + in ppc4xx_pciex_get_config_base()
1606 &ppc4xx_pciex_ports[hose->indirect_type]; in ppc4xx_pciex_read_config()
1610 BUG_ON(hose != port->hose); in ppc4xx_pciex_read_config()
1618 * Reading from configuration space of non-existing device can in ppc4xx_pciex_read_config()
1622 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG); in ppc4xx_pciex_read_config()
1623 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA); in ppc4xx_pciex_read_config()
1626 out_be32(port->utl_base + PEUTL_RCSTA, 0x00040000); in ppc4xx_pciex_read_config()
1640 pr_debug("pcie-config-read: bus=%3d [%3d..%3d] devfn=0x%04x" in ppc4xx_pciex_read_config()
1642 bus->number, hose->first_busno, hose->last_busno, in ppc4xx_pciex_read_config()
1646 if (in_be32(port->utl_base + PEUTL_RCSTA) & 0x00040000) { in ppc4xx_pciex_read_config()
1653 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg); in ppc4xx_pciex_read_config()
1663 &ppc4xx_pciex_ports[hose->indirect_type]; in ppc4xx_pciex_write_config()
1673 * Reading from configuration space of non-existing device can in ppc4xx_pciex_write_config()
1677 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG); in ppc4xx_pciex_write_config()
1678 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA); in ppc4xx_pciex_write_config()
1680 pr_debug("pcie-config-write: bus=%3d [%3d..%3d] devfn=0x%04x" in ppc4xx_pciex_write_config()
1682 bus->number, hose->first_busno, hose->last_busno, in ppc4xx_pciex_write_config()
1697 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg); in ppc4xx_pciex_write_config()
1722 (plb_addr & (size - 1)) != 0) { in ppc4xx_setup_one_pciex_POM()
1723 printk(KERN_WARNING "%pOF: Resource out of range\n", hose->dn); in ppc4xx_setup_one_pciex_POM()
1724 return -1; in ppc4xx_setup_one_pciex_POM()
1739 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAH, lah); in ppc4xx_setup_one_pciex_POM()
1740 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAL, lal); in ppc4xx_setup_one_pciex_POM()
1741 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKH, 0x7fffffff); in ppc4xx_setup_one_pciex_POM()
1743 if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx")) in ppc4xx_setup_one_pciex_POM()
1744 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, in ppc4xx_setup_one_pciex_POM()
1748 port->node, "ibm,plb-pciex-476fpe") || in ppc4xx_setup_one_pciex_POM()
1750 port->node, "ibm,plb-pciex-476gtr")) in ppc4xx_setup_one_pciex_POM()
1751 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, in ppc4xx_setup_one_pciex_POM()
1755 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, in ppc4xx_setup_one_pciex_POM()
1762 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAH, lah); in ppc4xx_setup_one_pciex_POM()
1763 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAL, lal); in ppc4xx_setup_one_pciex_POM()
1764 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKH, 0x7fffffff); in ppc4xx_setup_one_pciex_POM()
1765 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, in ppc4xx_setup_one_pciex_POM()
1771 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAH, lah); in ppc4xx_setup_one_pciex_POM()
1772 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAL, lal); in ppc4xx_setup_one_pciex_POM()
1773 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKH, 0x7fffffff); in ppc4xx_setup_one_pciex_POM()
1775 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, in ppc4xx_setup_one_pciex_POM()
1790 /* Setup outbound memory windows */ in ppc4xx_configure_pciex_POMs()
1792 struct resource *res = &hose->mem_resources[i]; in ppc4xx_configure_pciex_POMs()
1793 resource_size_t offset = hose->mem_offset[i]; in ppc4xx_configure_pciex_POMs()
1796 if (!(res->flags & IORESOURCE_MEM)) in ppc4xx_configure_pciex_POMs()
1800 port->node); in ppc4xx_configure_pciex_POMs()
1806 res->start, in ppc4xx_configure_pciex_POMs()
1807 res->start - offset, in ppc4xx_configure_pciex_POMs()
1809 res->flags, in ppc4xx_configure_pciex_POMs()
1816 if (res->start == offset) in ppc4xx_configure_pciex_POMs()
1822 if (j <= 1 && !found_isa_hole && hose->isa_mem_size) in ppc4xx_configure_pciex_POMs()
1824 hose->isa_mem_phys, 0, in ppc4xx_configure_pciex_POMs()
1825 hose->isa_mem_size, 0, j) == 0) in ppc4xx_configure_pciex_POMs()
1827 hose->dn); in ppc4xx_configure_pciex_POMs()
1830 * Note also that it -has- to be region index 2 on this HW in ppc4xx_configure_pciex_POMs()
1832 if (hose->io_resource.flags & IORESOURCE_IO) in ppc4xx_configure_pciex_POMs()
1834 hose->io_base_phys, 0, in ppc4xx_configure_pciex_POMs()
1846 if (port->endpoint) { in ppc4xx_configure_pciex_PIMs()
1876 if (res->flags & IORESOURCE_PREFETCH) in ppc4xx_configure_pciex_PIMs()
1879 if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx") || in ppc4xx_configure_pciex_PIMs()
1881 port->node, "ibm,plb-pciex-476fpe") || in ppc4xx_configure_pciex_PIMs()
1883 port->node, "ibm,plb-pciex-476gtr")) in ppc4xx_configure_pciex_PIMs()
1899 out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(res->start)); in ppc4xx_configure_pciex_PIMs()
1900 out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(res->start)); in ppc4xx_configure_pciex_PIMs()
1923 if (of_get_property(port->node, "primary", NULL)) in ppc4xx_pciex_port_setup_hose()
1927 bus_range = of_get_property(port->node, "bus-range", NULL); in ppc4xx_pciex_port_setup_hose()
1930 hose = pcibios_alloc_controller(port->node); in ppc4xx_pciex_port_setup_hose()
1937 hose->indirect_type = port->index; in ppc4xx_pciex_port_setup_hose()
1940 hose->first_busno = bus_range ? bus_range[0] : 0x0; in ppc4xx_pciex_port_setup_hose()
1941 hose->last_busno = bus_range ? bus_range[1] : 0xff; in ppc4xx_pciex_port_setup_hose()
1948 busses = hose->last_busno - hose->first_busno; /* This is off by 1 */ in ppc4xx_pciex_port_setup_hose()
1951 hose->last_busno = hose->first_busno + busses; in ppc4xx_pciex_port_setup_hose()
1954 if (!port->endpoint) { in ppc4xx_pciex_port_setup_hose()
1956 * PCIe root-complexes. External space is 1M per bus in ppc4xx_pciex_port_setup_hose()
1958 cfg_data = ioremap(port->cfg_space.start + in ppc4xx_pciex_port_setup_hose()
1959 (hose->first_busno + 1) * 0x100000, in ppc4xx_pciex_port_setup_hose()
1963 port->node); in ppc4xx_pciex_port_setup_hose()
1966 hose->cfg_data = cfg_data; in ppc4xx_pciex_port_setup_hose()
1972 mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000); in ppc4xx_pciex_port_setup_hose()
1975 port->node); in ppc4xx_pciex_port_setup_hose()
1978 hose->cfg_addr = mbase; in ppc4xx_pciex_port_setup_hose()
1980 pr_debug("PCIE %pOF, bus %d..%d\n", port->node, in ppc4xx_pciex_port_setup_hose()
1981 hose->first_busno, hose->last_busno); in ppc4xx_pciex_port_setup_hose()
1983 hose->cfg_addr, hose->cfg_data); in ppc4xx_pciex_port_setup_hose()
1986 hose->ops = &ppc4xx_pciex_pci_ops; in ppc4xx_pciex_port_setup_hose()
1987 port->hose = hose; in ppc4xx_pciex_port_setup_hose()
1988 mbase = (void __iomem *)hose->cfg_addr; in ppc4xx_pciex_port_setup_hose()
1990 if (!port->endpoint) { in ppc4xx_pciex_port_setup_hose()
1994 out_8(mbase + PCI_PRIMARY_BUS, hose->first_busno); in ppc4xx_pciex_port_setup_hose()
1995 out_8(mbase + PCI_SECONDARY_BUS, hose->first_busno + 1); in ppc4xx_pciex_port_setup_hose()
1996 out_8(mbase + PCI_SUBORDINATE_BUS, hose->last_busno); in ppc4xx_pciex_port_setup_hose()
2004 /* Parse outbound mapping resources */ in ppc4xx_pciex_port_setup_hose()
2005 pci_process_bridge_OF_ranges(hose, port->node, primary); in ppc4xx_pciex_port_setup_hose()
2011 /* Configure outbound ranges POMs */ in ppc4xx_pciex_port_setup_hose()
2020 * overwritten by setting the "vendor-id/device-id" properties in ppc4xx_pciex_port_setup_hose()
2024 /* Get the (optional) vendor-/device-id from the device-tree */ in ppc4xx_pciex_port_setup_hose()
2025 pval = of_get_property(port->node, "vendor-id", NULL); in ppc4xx_pciex_port_setup_hose()
2029 if (!port->endpoint) in ppc4xx_pciex_port_setup_hose()
2030 val = 0xaaa0 + port->index; in ppc4xx_pciex_port_setup_hose()
2032 val = 0xeee0 + port->index; in ppc4xx_pciex_port_setup_hose()
2036 pval = of_get_property(port->node, "device-id", NULL); in ppc4xx_pciex_port_setup_hose()
2040 if (!port->endpoint) in ppc4xx_pciex_port_setup_hose()
2041 val = 0xbed0 + port->index; in ppc4xx_pciex_port_setup_hose()
2043 val = 0xfed0 + port->index; in ppc4xx_pciex_port_setup_hose()
2048 if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx")) in ppc4xx_pciex_port_setup_hose()
2051 if (!port->endpoint) { in ppc4xx_pciex_port_setup_hose()
2052 /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */ in ppc4xx_pciex_port_setup_hose()
2055 printk(KERN_INFO "PCIE%d: successfully set as root-complex\n", in ppc4xx_pciex_port_setup_hose()
2056 port->index); in ppc4xx_pciex_port_setup_hose()
2062 port->index); in ppc4xx_pciex_port_setup_hose()
2088 /* Get the port number from the device-tree */ in ppc4xx_probe_pciex_bridge()
2101 port->index = portno; in ppc4xx_probe_pciex_bridge()
2107 printk(KERN_INFO "PCIE%d: Port disabled via device-tree\n", port->index); in ppc4xx_probe_pciex_bridge()
2111 port->node = of_node_get(np); in ppc4xx_probe_pciex_bridge()
2112 if (ppc4xx_pciex_hwops->want_sdr) { in ppc4xx_probe_pciex_bridge()
2113 pval = of_get_property(np, "sdr-base", NULL); in ppc4xx_probe_pciex_bridge()
2115 printk(KERN_ERR "PCIE: missing sdr-base for %pOF\n", in ppc4xx_probe_pciex_bridge()
2119 port->sdr_base = *pval; in ppc4xx_probe_pciex_bridge()
2122 /* Check if device_type property is set to "pci" or "pci-endpoint". in ppc4xx_probe_pciex_bridge()
2124 * as root-complex or as endpoint. in ppc4xx_probe_pciex_bridge()
2126 if (of_node_is_type(port->node, "pci-endpoint")) { in ppc4xx_probe_pciex_bridge()
2127 port->endpoint = 1; in ppc4xx_probe_pciex_bridge()
2128 } else if (of_node_is_type(port->node, "pci")) { in ppc4xx_probe_pciex_bridge()
2129 port->endpoint = 0; in ppc4xx_probe_pciex_bridge()
2137 if (of_address_to_resource(np, 0, &port->cfg_space)) { in ppc4xx_probe_pciex_bridge()
2138 printk(KERN_ERR "%pOF: Can't get PCI-E config space !", np); in ppc4xx_probe_pciex_bridge()
2142 if (of_address_to_resource(np, 1, &port->utl_regs)) { in ppc4xx_probe_pciex_bridge()
2153 port->dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0)); in ppc4xx_probe_pciex_bridge()
2157 printk(KERN_WARNING "PCIE%d: Port init failed\n", port->index); in ppc4xx_probe_pciex_bridge()
2174 for_each_compatible_node(np, NULL, "ibm,plb-pciex") in ppc4xx_pci_find_bridges()
2177 for_each_compatible_node(np, NULL, "ibm,plb-pcix") in ppc4xx_pci_find_bridges()
2179 for_each_compatible_node(np, NULL, "ibm,plb-pci") in ppc4xx_pci_find_bridges()