Lines Matching +full:1 +full:c
40 * MMCR1[25] = pmc1combine[1]
42 * MMCR1[27] = pmc2combine[1]
44 * MMCR1[29] = pmc3combine[1]
46 * MMCR1[31] = pmc4combine[1]
66 * MMCRA[63] = 1 (SAMPLE_ENABLE)
283 return -1; in power9_bhrb_filter_map()
286 return -1; in power9_bhrb_filter_map()
289 return -1; in power9_bhrb_filter_map()
297 return -1; in power9_bhrb_filter_map()
308 #define C(x) PERF_COUNT_HW_CACHE_##x macro
312 * 0 means not supported, -1 means nonsensical, other values
315 static u64 power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
316 [ C(L1D) ] = {
317 [ C(OP_READ) ] = {
318 [ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
319 [ C(RESULT_MISS) ] = PM_LD_MISS_L1_FIN,
321 [ C(OP_WRITE) ] = {
322 [ C(RESULT_ACCESS) ] = 0,
323 [ C(RESULT_MISS) ] = PM_ST_MISS_L1,
325 [ C(OP_PREFETCH) ] = {
326 [ C(RESULT_ACCESS) ] = PM_L1_PREF,
327 [ C(RESULT_MISS) ] = 0,
330 [ C(L1I) ] = {
331 [ C(OP_READ) ] = {
332 [ C(RESULT_ACCESS) ] = PM_INST_FROM_L1,
333 [ C(RESULT_MISS) ] = PM_L1_ICACHE_MISS,
335 [ C(OP_WRITE) ] = {
336 [ C(RESULT_ACCESS) ] = PM_L1_DEMAND_WRITE,
337 [ C(RESULT_MISS) ] = -1,
339 [ C(OP_PREFETCH) ] = {
340 [ C(RESULT_ACCESS) ] = PM_IC_PREF_WRITE,
341 [ C(RESULT_MISS) ] = 0,
344 [ C(LL) ] = {
345 [ C(OP_READ) ] = {
346 [ C(RESULT_ACCESS) ] = PM_DATA_FROM_L3,
347 [ C(RESULT_MISS) ] = PM_DATA_FROM_L3MISS,
349 [ C(OP_WRITE) ] = {
350 [ C(RESULT_ACCESS) ] = 0,
351 [ C(RESULT_MISS) ] = 0,
353 [ C(OP_PREFETCH) ] = {
354 [ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL,
355 [ C(RESULT_MISS) ] = 0,
358 [ C(DTLB) ] = {
359 [ C(OP_READ) ] = {
360 [ C(RESULT_ACCESS) ] = 0,
361 [ C(RESULT_MISS) ] = PM_DTLB_MISS,
363 [ C(OP_WRITE) ] = {
364 [ C(RESULT_ACCESS) ] = -1,
365 [ C(RESULT_MISS) ] = -1,
367 [ C(OP_PREFETCH) ] = {
368 [ C(RESULT_ACCESS) ] = -1,
369 [ C(RESULT_MISS) ] = -1,
372 [ C(ITLB) ] = {
373 [ C(OP_READ) ] = {
374 [ C(RESULT_ACCESS) ] = 0,
375 [ C(RESULT_MISS) ] = PM_ITLB_MISS,
377 [ C(OP_WRITE) ] = {
378 [ C(RESULT_ACCESS) ] = -1,
379 [ C(RESULT_MISS) ] = -1,
381 [ C(OP_PREFETCH) ] = {
382 [ C(RESULT_ACCESS) ] = -1,
383 [ C(RESULT_MISS) ] = -1,
386 [ C(BPU) ] = {
387 [ C(OP_READ) ] = {
388 [ C(RESULT_ACCESS) ] = PM_BR_CMPL,
389 [ C(RESULT_MISS) ] = PM_BR_MPRED_CMPL,
391 [ C(OP_WRITE) ] = {
392 [ C(RESULT_ACCESS) ] = -1,
393 [ C(RESULT_MISS) ] = -1,
395 [ C(OP_PREFETCH) ] = {
396 [ C(RESULT_ACCESS) ] = -1,
397 [ C(RESULT_MISS) ] = -1,
400 [ C(NODE) ] = {
401 [ C(OP_READ) ] = {
402 [ C(RESULT_ACCESS) ] = -1,
403 [ C(RESULT_MISS) ] = -1,
405 [ C(OP_WRITE) ] = {
406 [ C(RESULT_ACCESS) ] = -1,
407 [ C(RESULT_MISS) ] = -1,
409 [ C(OP_PREFETCH) ] = {
410 [ C(RESULT_ACCESS) ] = -1,
411 [ C(RESULT_MISS) ] = -1,
416 #undef C
454 if ((PVR_CFG(pvr) == 2) && (PVR_MIN(pvr) == 1)) { in init_power9_pmu()