powerpc/perf/power8-pmu.c

1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #define pr_fmt(fmt)	"power8-pmu: " fmt
11 #include "isa207-common.h"
14  * Some power8 event codes.
16 #define EVENT(_name, _code)	_name = _code,  macro
19 #include "power8-events-list.h"
22 #undef EVENT
24 /* MMCRA IFM bits - POWER8 */
31  * Raw event encoding for PowerISA v2.07 (Power8):
34  * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
37  *   | |  *- IFM (Linux)                 thresh start/stop OR FAB match -*
38  *   | *- BHRB (Linux)
39  *   *- EBB (Linux)
42  * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
45  *     |        |           |                          |     *- mark
46  *     |        |           *- L1/L2/L3 cache_sel      |
48  *     |        *- sampling mode for marked events     *- combine
50  *     *- thresh_sel
80  * else if cache_sel[1]: # L1 event
112 static int power8_get_alternatives(u64 event, unsigned int flags, u64 alt[])  in power8_get_alternatives()  argument
116 	num_alt = isa207_get_alternatives(event, alt,  in power8_get_alternatives()
123 GENERIC_EVENT_ATTR(cpu-cycles,			PM_CYC);
124 GENERIC_EVENT_ATTR(stalled-cycles-frontend,	PM_GCT_NOSLOT_CYC);
125 GENERIC_EVENT_ATTR(stalled-cycles-backend,	PM_CMPLU_STALL);
127 GENERIC_EVENT_ATTR(branch-instructions,		PM_BRU_FIN);
128 GENERIC_EVENT_ATTR(branch-misses,		PM_BR_MPRED_CMPL);
129 GENERIC_EVENT_ATTR(cache-references,		PM_LD_REF_L1);
130 GENERIC_EVENT_ATTR(cache-misses,		PM_LD_MISS_L1);
133 CACHE_EVENT_ATTR(L1-dcache-load-misses,		PM_LD_MISS_L1);
134 CACHE_EVENT_ATTR(L1-dcache-loads,		PM_LD_REF_L1);
136 CACHE_EVENT_ATTR(L1-dcache-prefetches,		PM_L1_PREF);
137 CACHE_EVENT_ATTR(L1-dcache-store-misses,	PM_ST_MISS_L1);
138 CACHE_EVENT_ATTR(L1-icache-load-misses,		PM_L1_ICACHE_MISS);
139 CACHE_EVENT_ATTR(L1-icache-loads,		PM_INST_FROM_L1);
140 CACHE_EVENT_ATTR(L1-icache-prefetches,		PM_IC_PREF_WRITE);
142 CACHE_EVENT_ATTR(LLC-load-misses,		PM_DATA_FROM_L3MISS);
143 CACHE_EVENT_ATTR(LLC-loads,			PM_DATA_FROM_L3);
144 CACHE_EVENT_ATTR(LLC-prefetches,		PM_L3_PREF_ALL);
145 CACHE_EVENT_ATTR(LLC-store-misses,		PM_L2_ST_MISS);
146 CACHE_EVENT_ATTR(LLC-stores,			PM_L2_ST);
148 CACHE_EVENT_ATTR(branch-load-misses,		PM_BR_MPRED_CMPL);
149 CACHE_EVENT_ATTR(branch-loads,			PM_BRU_FIN);
150 CACHE_EVENT_ATTR(dTLB-load-misses,		PM_DTLB_MISS);
151 CACHE_EVENT_ATTR(iTLB-load-misses,		PM_ITLB_MISS);
213 	 * regular PMU event. As the privilege state filter is handled  in power8_bhrb_filter_map()
215 	 * PMU event, we ignore any separate BHRB specific request.  in power8_bhrb_filter_map()
222 	/* Invalid branch filter options - HW does not support */  in power8_bhrb_filter_map()
224 		return -1;  in power8_bhrb_filter_map()
227 		return -1;  in power8_bhrb_filter_map()
230 		return -1;  in power8_bhrb_filter_map()
238 	return -1;  in power8_bhrb_filter_map()
252  * Table of generalized cache-related events.
253  * 0 means not supported, -1 means nonsensical, other values
254  * are event codes.
278 			[ C(RESULT_MISS)   ] = -1,
305 			[ C(RESULT_ACCESS) ] = -1,
306 			[ C(RESULT_MISS)   ] = -1,
309 			[ C(RESULT_ACCESS) ] = -1,
310 			[ C(RESULT_MISS)   ] = -1,
319 			[ C(RESULT_ACCESS) ] = -1,
320 			[ C(RESULT_MISS)   ] = -1,
323 			[ C(RESULT_ACCESS) ] = -1,
324 			[ C(RESULT_MISS)   ] = -1,
333 			[ C(RESULT_ACCESS) ] = -1,
334 			[ C(RESULT_MISS)   ] = -1,
337 			[ C(RESULT_ACCESS) ] = -1,
338 			[ C(RESULT_MISS)   ] = -1,
343 			[ C(RESULT_ACCESS) ] = -1,
344 			[ C(RESULT_MISS)   ] = -1,
347 			[ C(RESULT_ACCESS) ] = -1,
348 			[ C(RESULT_MISS)   ] = -1,
351 			[ C(RESULT_ACCESS) ] = -1,
352 			[ C(RESULT_MISS)   ] = -1,
385 	if (!cur_cpu_spec->oprofile_cpu_type ||  in init_power8_pmu()
386 	    strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power8"))  in init_power8_pmu()
387 		return -ENODEV;  in init_power8_pmu()
394 	cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB;  in init_power8_pmu()