Lines Matching +full:1 +full:c
39 * MMCR1[25] = pmc1combine[1]
41 * MMCR1[27] = pmc2combine[1]
43 * MMCR1[29] = pmc3combine[1]
45 * MMCR1[31] = pmc4combine[1]
61 * MMCR1[17] = cache_sel[1]
64 * MMCRA[63] = 1 (SAMPLE_ENABLE)
71 * MMCRA[SDAR_MODE] = sdar_mode[0:1]
237 return -1; in power10_bhrb_filter_map()
250 return -1; in power10_bhrb_filter_map()
258 return -1; in power10_bhrb_filter_map()
269 #define C(x) PERF_COUNT_HW_CACHE_##x macro
273 * 0 means not supported, -1 means nonsensical, other values
276 static u64 power10_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
277 [C(L1D)] = {
278 [C(OP_READ)] = {
279 [C(RESULT_ACCESS)] = PM_LD_REF_L1,
280 [C(RESULT_MISS)] = PM_LD_MISS_L1,
282 [C(OP_WRITE)] = {
283 [C(RESULT_ACCESS)] = 0,
284 [C(RESULT_MISS)] = PM_ST_MISS_L1,
286 [C(OP_PREFETCH)] = {
287 [C(RESULT_ACCESS)] = PM_LD_PREFETCH_CACHE_LINE_MISS,
288 [C(RESULT_MISS)] = 0,
291 [C(L1I)] = {
292 [C(OP_READ)] = {
293 [C(RESULT_ACCESS)] = PM_INST_FROM_L1,
294 [C(RESULT_MISS)] = PM_L1_ICACHE_MISS,
296 [C(OP_WRITE)] = {
297 [C(RESULT_ACCESS)] = PM_INST_FROM_L1MISS,
298 [C(RESULT_MISS)] = -1,
300 [C(OP_PREFETCH)] = {
301 [C(RESULT_ACCESS)] = PM_IC_PREF_REQ,
302 [C(RESULT_MISS)] = 0,
305 [C(LL)] = {
306 [C(OP_READ)] = {
307 [C(RESULT_ACCESS)] = PM_DATA_FROM_L3,
308 [C(RESULT_MISS)] = PM_DATA_FROM_L3MISS,
310 [C(OP_WRITE)] = {
311 [C(RESULT_ACCESS)] = -1,
312 [C(RESULT_MISS)] = -1,
314 [C(OP_PREFETCH)] = {
315 [C(RESULT_ACCESS)] = -1,
316 [C(RESULT_MISS)] = 0,
319 [C(DTLB)] = {
320 [C(OP_READ)] = {
321 [C(RESULT_ACCESS)] = 0,
322 [C(RESULT_MISS)] = PM_DTLB_MISS,
324 [C(OP_WRITE)] = {
325 [C(RESULT_ACCESS)] = -1,
326 [C(RESULT_MISS)] = -1,
328 [C(OP_PREFETCH)] = {
329 [C(RESULT_ACCESS)] = -1,
330 [C(RESULT_MISS)] = -1,
333 [C(ITLB)] = {
334 [C(OP_READ)] = {
335 [C(RESULT_ACCESS)] = 0,
336 [C(RESULT_MISS)] = PM_ITLB_MISS,
338 [C(OP_WRITE)] = {
339 [C(RESULT_ACCESS)] = -1,
340 [C(RESULT_MISS)] = -1,
342 [C(OP_PREFETCH)] = {
343 [C(RESULT_ACCESS)] = -1,
344 [C(RESULT_MISS)] = -1,
347 [C(BPU)] = {
348 [C(OP_READ)] = {
349 [C(RESULT_ACCESS)] = PM_BR_CMPL,
350 [C(RESULT_MISS)] = PM_BR_MPRED_CMPL,
352 [C(OP_WRITE)] = {
353 [C(RESULT_ACCESS)] = -1,
354 [C(RESULT_MISS)] = -1,
356 [C(OP_PREFETCH)] = {
357 [C(RESULT_ACCESS)] = -1,
358 [C(RESULT_MISS)] = -1,
361 [C(NODE)] = {
362 [C(OP_READ)] = {
363 [C(RESULT_ACCESS)] = -1,
364 [C(RESULT_MISS)] = -1,
366 [C(OP_WRITE)] = {
367 [C(RESULT_ACCESS)] = -1,
368 [C(RESULT_MISS)] = -1,
370 [C(OP_PREFETCH)] = {
371 [C(RESULT_ACCESS)] = -1,
372 [C(RESULT_MISS)] = -1,
377 #undef C