Lines Matching +full:1 +full:c
29 * 1: can go on PMCs 1-4
30 * 2: can go on PMCs 1,2,4
31 * 3: can go on PMCs 1 or 2
33 * -1: event code is invalid
44 return -1; in mpc7450_classify_event()
48 if (event <= 1) in mpc7450_classify_event()
51 return 1; in mpc7450_classify_event()
56 return -1; in mpc7450_classify_event()
67 * 30c N PM_GPR_RB_EXCEED_CYC
75 * 0 = uses neither, 1 = uses threshold, 2 = uses both
84 case 1: in mpc7450_threshold_use()
86 return 1; in mpc7450_threshold_use()
92 return 1; in mpc7450_threshold_use()
96 return 1; in mpc7450_threshold_use()
102 return 1; in mpc7450_threshold_use()
143 static u32 classbits[N_CLASSES - 1][2] = {
145 { 0x00800000, 0x00100000 }, /* class 1: G4 */
159 return -1; in mpc7450_get_constraint()
162 mask = pmcbits[pmc - 1][0]; in mpc7450_get_constraint()
163 value = pmcbits[pmc - 1][1]; in mpc7450_get_constraint()
166 value = classbits[class][1]; in mpc7450_get_constraint()
206 * index into the alternatives table if found, else -1.
219 return -1; in find_alternative()
224 int i, j, nalt = 1; in mpc7450_get_alternatives()
228 nalt = 1; in mpc7450_get_alternatives()
242 * Bit i is set if PMC i+1 is usable.
257 * Compute MMCR0/1/2 values for a set of events.
271 return -1; in mpc7450_compute_mmcr()
279 return -1; in mpc7450_compute_mmcr()
285 for (class = N_CLASSES - 1; class >= 0; --class) { in mpc7450_compute_mmcr()
290 if (pmc_inuse & (1 << (pmc - 1))) in mpc7450_compute_mmcr()
291 return -1; in mpc7450_compute_mmcr()
296 return -1; in mpc7450_compute_mmcr()
299 pmc_inuse |= 1 << (pmc - 1); in mpc7450_compute_mmcr()
308 ev &= pmcsel_mask[pmc - 1]; in mpc7450_compute_mmcr()
309 ev <<= pmcsel_shift[pmc - 1]; in mpc7450_compute_mmcr()
314 hwc[event_index[class][i]] = pmc - 1; in mpc7450_compute_mmcr()
318 if (pmc_inuse & 1) in mpc7450_compute_mmcr()
339 * Note that the pmc argument is 0-based here, not 1-based.
343 if (pmc <= 1) in mpc7450_disable_pmc()
350 [PERF_COUNT_HW_CPU_CYCLES] = 1,
357 #define C(x) PERF_COUNT_HW_CACHE_##x macro
361 * 0 means not supported, -1 means nonsensical, other values
364 static u64 mpc7450_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
365 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
366 [C(OP_READ)] = { 0, 0x225 },
367 [C(OP_WRITE)] = { 0, 0x227 },
368 [C(OP_PREFETCH)] = { 0, 0 },
370 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
371 [C(OP_READ)] = { 0x129, 0x115 },
372 [C(OP_WRITE)] = { -1, -1 },
373 [C(OP_PREFETCH)] = { 0x634, 0 },
375 [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
376 [C(OP_READ)] = { 0, 0 },
377 [C(OP_WRITE)] = { 0, 0 },
378 [C(OP_PREFETCH)] = { 0, 0 },
380 [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */
381 [C(OP_READ)] = { 0, 0x312 },
382 [C(OP_WRITE)] = { -1, -1 },
383 [C(OP_PREFETCH)] = { -1, -1 },
385 [C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */
386 [C(OP_READ)] = { 0, 0x223 },
387 [C(OP_WRITE)] = { -1, -1 },
388 [C(OP_PREFETCH)] = { -1, -1 },
390 [C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */
391 [C(OP_READ)] = { 0x122, 0x41c },
392 [C(OP_WRITE)] = { -1, -1 },
393 [C(OP_PREFETCH)] = { -1, -1 },
395 [C(NODE)] = { /* RESULT_ACCESS RESULT_MISS */
396 [C(OP_READ)] = { -1, -1 },
397 [C(OP_WRITE)] = { -1, -1 },
398 [C(OP_PREFETCH)] = { -1, -1 },