1 // SPDX-License-Identifier: GPL-2.0-or-later
22 #include <asm/cell-pmu.h>
32 #include <asm/cell-regs.h>
66  * 2^32 - 1 - N.
68 #define NUM_INTERVAL_CYC  0xFFFFFFFF - 10
73  * at the beginning of cell_reg_setup; otherwise, it's read-only.
87  * ibm,cbe-perftools rtas parameters
94 				 * Bus Word(s) (bitmask)
157  * 0 - even virtual cpus 0, 2, 4,...
158  * 1 - odd virtual cpus 1, 3, 5, ...
161  * of places. It works for now. -arnd
272 			return -EIO;  in pm_rtas_activate_signals()
293 		p->signal_group = PPU_CYCLES_GRP_NUM;  in set_pm_event()
294 		p->bus_word = 1;  in set_pm_event()
295 		p->sub_unit = 0;  in set_pm_event()
296 		p->bit = 0;  in set_pm_event()
311 	p->signal_group = event / 100;  in set_pm_event()
312 	p->bus_word = bus_word;  in set_pm_event()
313 	p->sub_unit = GET_SUB_UNIT(unit_mask);  in set_pm_event()
322 	 * The debug bus words are 32 bits, the input words to the performance  in set_pm_event()
323 	 * counters are defined as 32 bits.  Need to convert the 64 bit island  in set_pm_event()
324 	 * specification to the appropriate 32 input bit and bus word for the  in set_pm_event()
331 			signal_bit -= 32;  in set_pm_event()
338 		if ((bus_type == 0) && p->signal_group >= 60)  in set_pm_event()
340 		if ((bus_type == 1) && p->signal_group >= 50)  in set_pm_event()
346 		p->bit = signal_bit;  in set_pm_event()
352 				(bus_type << (30 - (2 * i)));  in set_pm_event()
358 						(i << (30 - (2 * j)));  in set_pm_event()
372 	 * Oprofile will use 32 bit counters, set bits 7:10 to 0  in write_pm_cntrl()
433  * However, there is one set of performance counters per node.	There are
439  * The pmc_values used below is defined as 'per-cpu' but its use is
440  * more akin to 'per-node'.  We need to store two sets of counter
441  * values per node -- one for the previous run and one for the next.
442  * The per-cpu[NR_PHYS_CTRS] gives us the storage we need.  Each odd/even
443  * pair of per-cpu arrays is used for storing the previous and next
445  * NOTE: We use the per-cpu variable to improve cache performance.
476 	 * There are some per thread events.  Must do the  in cell_virtual_cntr()
485 	 * The following is done only once per each node, but  in cell_virtual_cntr()
508 				 * restore the counters to the max value.  If  in cell_virtual_cntr()
509 				 * the counters were restored to the max value,  in cell_virtual_cntr()
530 				 * There are some per thread events.  in cell_virtual_cntr()
568 	spu_rtas_token = rtas_token("ibm,cbe-spu-perftools");  in cell_reg_setup_spu_cycles()
572 		       "%s: rtas token ibm,cbe-spu-perftools unknown\n",  in cell_reg_setup_spu_cycles()
574 		return -EIO;  in cell_reg_setup_spu_cycles()
580  * on one SPU per node at a time.  Therefore, we must time slice
638 		 * counter value is at max (0xFFFFFFFF).  in spu_evnt_swap()
691 	 * the rtas cbe-perftools call to setup and reset the debug bus.  in cell_reg_setup_spu_events()
695 	pm_rtas_token = rtas_token("ibm,cbe-perftools");  in cell_reg_setup_spu_events()
699 		       "%s: rtas token ibm,cbe-perftools unknown\n",  in cell_reg_setup_spu_events()
701 		return -EIO;  in cell_reg_setup_spu_events()
705 	 * settings will be written per node by the  in cell_reg_setup_spu_events()
738 	reset_value[0] = 0xFFFFFFFF - ctr[0].count;  in cell_reg_setup_spu_events()
763 		return -EIO;  in cell_reg_setup_ppu()
766 	set_count_mode(sys->enable_kernel, sys->enable_user);  in cell_reg_setup_ppu()
812 			/* Using 32bit counters, reset max - count */  in cell_reg_setup_ppu()
813 			reset_value[i] = 0xFFFFFFFF - ctr[i].count;  in cell_reg_setup_ppu()
853 	 * the rtas cbe-perftools call to setup and reset the debug bus.  in cell_reg_setup()
857 	pm_rtas_token = rtas_token("ibm,cbe-perftools");  in cell_reg_setup()
861 		       "%s: rtas token ibm,cbe-perftools unknown\n",  in cell_reg_setup()
863 		return -EIO;  in cell_reg_setup()
906 	/* There is one performance monitor per processor chip (i.e. node),  in cell_cpu_setup()
907 	 * so we only need to perform this function once per node.  in cell_cpu_setup()
929 	 * The pm_rtas_activate_signals will return -EIO if the FW  in cell_cpu_setup()
1012  * 0		    to	2^16-1			----		      0
1013  * 2^16	    to	2^16+2^19-1		2^12		    1 to 128
1014  * 2^16+2^19	    to	2^16+2^19+2^22-1	2^15		  129 to 256
1015  * 2^16+2^19+2^22  to	2^24-1			2^18		  257 to 302
1019  * 2^16+2^12, ... , 2^19-2^16, 2^19 and stored in the table at indicies
1034  *		newlfsr0 = (((lfsr >> (size - 1 - 0)) & 1) ^
1035  *		((lfsr >> (size - 1 - 1)) & 1) ^
1036  *		(((lfsr >> (size - 1 - 6)) & 1) ^
1037  *		((lfsr >> (size - 1 - 23)) & 1)));
1040  *		lfsr = lfsr | (newlfsr0 << (size - 1));
1060 	else if (((n - V2_16) >> 19) == 0)  in calculate_lfsr()
1061 		index = ((n - V2_16) >> 12) + 1;  in calculate_lfsr()
1062 	else if (((n - V2_16 - V2_19) >> 22) == 0)  in calculate_lfsr()
1063 		index = ((n - V2_16 - V2_19) >> 15 ) + 1 + 128;  in calculate_lfsr()
1064 	else if (((n - V2_16 - V2_19 - V2_22) >> 24) == 0)  in calculate_lfsr()
1065 		index = ((n - V2_16 - V2_19 - V2_22) >> 18 ) + 1 + 256;  in calculate_lfsr()
1067 		index = ENTRIES-1;  in calculate_lfsr()
1071 		index = ENTRIES-1;  in calculate_lfsr()
1088 		/* spu i on word (i/2) */  in pm_rtas_activate_spu_profiling()
1103 		return -EIO;  in pm_rtas_activate_spu_profiling()
1115 	if ((val == CPUFREQ_PRECHANGE && frq->old < frq->new) ||  in oprof_cpufreq_notify()
1116 	    (val == CPUFREQ_POSTCHANGE && frq->old > frq->new))  in oprof_cpufreq_notify()
1117 		set_spu_profiling_frequency(frq->new, spu_cycle_reset);  in oprof_cpufreq_notify()
1153 				 * 2 - activate SPU tracing,  in cell_global_stop_spu_cycles()
1154 				 * 3 - deactivate  in cell_global_stop_spu_cycles()
1164 			       "%s: rtas call ibm,cbe-spu-perftools " \  in cell_global_stop_spu_cycles()
1208 	 * There is one performance monitor per node, so we  in cell_global_stop_ppu()
1209 	 * only need to perform this function once per node.  in cell_global_stop_ppu()
1250 	/* The SPU profiling uses time-based profiling based on  in cell_global_start_spu_cycles()
1274 		 * Setup SPU cycle-based profiling.  in cell_global_start_spu_cycles()
1282 			lfsr_value = calculate_lfsr(MAX_SPU_COUNT-1);  in cell_global_start_spu_cycles()
1303 		subfunc = 2;	/* 2 - activate SPU tracing, 3 - deactivate */  in cell_global_start_spu_cycles()
1311 			       "%s: rtas call ibm,cbe-spu-perftools failed, " \  in cell_global_start_spu_cycles()
1313 			rtas_error = -EIO;  in cell_global_start_spu_cycles()
1342 	 * enable storing data to the trace buffer.  The bits are set  in cell_global_start_spu_events()
1349 	 * There is one performance monitor per node, so we  in cell_global_start_spu_events()
1350 	 * only need to perform this function once per node.  in cell_global_start_spu_events()
1358 		 * Setup SPU event-based profiling.  in cell_global_start_spu_events()
1362 		 * Only support one SPU event on one SPU per node.  in cell_global_start_spu_events()
1384 	 * per node at a time.  in cell_global_start_spu_events()
1400 	 * There is one performance monitor per node, so we  in cell_global_start_ppu()
1401 	 * only need to perform this function once per node.  in cell_global_start_ppu()
1433 	 * the above for-loop.  in cell_global_start_ppu()
1455  * the debug bus using word 0 or 1.  The value of pm_signal[1] and
1461  * initialized to the max hardware count minus the number of events, N, between
1470  * is cleared, interrupts are cleared, the counter is reset to max - N.
1534 		 *    HDR bits          0:15  in cell_handle_interrupt_spu()
1535 		 *    SPU Addr 0 bits   16:31  in cell_handle_interrupt_spu()
1536 		 *    SPU Addr 1 bits   32:47  in cell_handle_interrupt_spu()
1537 		 *    unused bits       48:127  in cell_handle_interrupt_spu()
1541 		 *  - unfortunately, the valid bits don't seem to work  in cell_handle_interrupt_spu()
1543 		 * Note trace_buffer[0] holds bits 0:63 of the HW  in cell_handle_interrupt_spu()
1544 		 * trace buffer, trace_buffer[1] holds bits 64:127  in cell_handle_interrupt_spu()
1552 		 * by 16 -2 bits */  in cell_handle_interrupt_spu()
1578 		/* clear the trace buffer, re-enable writes to trace buff */  in cell_handle_interrupt_spu()
1583 		 * to a latch.  The new values (interrupt setting bits, reset  in cell_handle_interrupt_spu()
1633 		pc = regs->nip;  in cell_handle_interrupt_ppu()
1650 		 * use the virt_cntr_inter_mask to re-enable the interrupts.  in cell_handle_interrupt_ppu()
1657 		 * to a latch.	The new values (interrupt setting bits, reset  in cell_handle_interrupt_ppu()